| Commit message (Collapse) | Author | Age | Files | Lines |
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Provide it also if RTEMS_MULTIPROCESSING is defined.
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Some includes may use C++ and this conflicts if surrounded extern "C".
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Check that data cache snooping exists and is enabled on all cores.
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Manupilating the interrupt control registers directly instead
of going through the interrupt layer can be deceiving.
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Changed LEON3_irq-mp to const also.
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The LEON2 and ERC32 maps the new macros to CPU0 since they do not
support SMP. With the LEON3 a specific CPU's interrupt controller
registers can be modified using macros.
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Move interrupt lock to device context and expose only this structure to
the read, write and set attributes device handler. This makes these
device handler independent of the general Termios infrastructure
suitable for direct use in printk() support.
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Now that a SPARC fatal handler is defined, we no longer
need the BSP specific reset routine.
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By removing the bsp_reset() mechanism and instead relying on the
CPU_Fatal_halt() routine SMP and single-core can halt by updating
the _Internal_errors_What_happened structure and set the state to
SYSTEM_STATE_TERMINATED (the generic way). This will be better
for test scripts and debugger that can generically look into why
the OS stopped.
For SMP systems, only the fatal-reporting CPU waits until all other
CPUs are powered down (with a time out of one clock tick). The
reason why a fatal stop happend may be because CPU0 was soft-locked
up so we can never trust that CPU0 should do the halt for us.
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The Fatal_halt handler now have two options, either halt
as before or enter system error state to return to
debugger or simulator. The exit-code is now also
propagated to the debugger which is very useful for
testing.
The CPU_Fatal_halt handler was split up into two, since
the only the LEON3 support the CPU power down.
The LEON3 halt now uses the power-down instruction to save
CPU power. This doesn't stop a potential watch-dog timer
from expiring.
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Instead of calling the system call TA instruction directly it
is better paractise to isolate the trap implementation to the
system call functions.
BSP_fatal_exit() is added.
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The LEON3_MP_IRQ define is used to pick the IRQ to be used by the
shared memory driver and for inter-processor interrupts. On some LEON3
systems, for example the GR712RC, the default value of 14 is not suitable.
To make this value configurable from the application, it is replaced with
a weakly linked variable that can be overridden from the application.
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This change starts with removing the effectively empty file
timerdrv.h. The prototypes for benchmark_timer_XXX() were in
btimer.h which was not universally used. Thus every use of
timerdrv.h had to be changed to btimer.h. Then the prototypes
for benchmark_timer_read() had to be adjusted to return
benchmark_timer_t rather than int or uint32_t.
I took this opportunity to also correct the file headers to
separate the copyright from the file description comments which
is needed to ensure the copyright isn't propagated into Doxygen
output.
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Rename _BSP_Exception_frame_print() to _CPU_Exception_frame_print() to
be in line with other CPU port functions.
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Rename _BSP_Start_multitasking to _LEON3_Start_multitasking to show that
it is LEON specific
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There is support for the LEON3 processor available in Binutils 2.24 and
the GCC 4.8 branch and GCC mainline.
GCC 4.8 branch:
http://gcc.gnu.org/viewcvs/gcc/branches/?view=log&pathrev=205331
GCC mainline:
http://gcc.gnu.org/viewcvs/gcc/trunk/?view=log&pathrev=202664
It is mandatory to use this option for SMP on LEON3 since it enables
usage of C11 atomic operations. It makes it also possible to use an
inline function for _CPU_SMP_Get_current_processor() which avoids the
function call overhead in critical sections.
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With this patch the preinstall.am files are in a set order and not
dependent on now perl implements a hash.
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Apparently, at some point automake output changed and these were
not updated.
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Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is
defined the instruction cache invalidation function will perform the
operation on all cores using the previous method.
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The flush instruction on LEON flushes both the data and the instruction
cache. Flushing of just the instruction cache can be done by setting
the "flush instruction cache" bit in the cache control register.
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A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.
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This prevents failures of all tests using rtems_shell_wait_for_input(),
e.g. capture, termios, pppd, etc.
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Move the APBUART console driver support to the shared SPARC area so that
it can be reused by other BSPs. Only the console driver initialization
is now BSP specific.
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Fix context switch on SMP for ARM, PowerPC and SPARC.
Atomically test and set the is executing indicator of the heir context
to ensure that at most one processor uses the heir context. Break the
busy wait loop also due to heir updates.
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.. according to the maximum number of termios ports which is
8. Since LEON3 uses PnP to find how many UARTs there are
present we must make sure worst case work.
The current maximum of 4 free nodes caused for example the
GR712RC with its 6 UARTs to fail during devfs02 test.
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On SMP rtems_interrupt_lock_context must be used. Most tests fail with a
NULL pointer exception when exiting, except on NGMP where main memory is
at 0x00000000.
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Guest systems in paravirtualization environments run usually in user
mode. Thus it is not possible to directly access the PSR and TBR
registers. Use functions instead of inline assembler to access these
registers if RTEMS_PARAVIRT is defined.
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The last optimization missed was incorrect in regards to
PSR write instruction delay must be 3 instructions.
New optimizations:
* align to 32-byte cache line.
* rearrange code into three "blocks" of 4 instructions that
is executed by syscall 2 and 3. This is to optimize for
16/32 byte cache lines.
* use delay-slot instruction in trap table to reduce by one
instruction.
* use the fact that "wr %PSR" implements XOR to reduce by
one instruction.
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