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* SPARC: optimize IRQ enable & disableDaniel Hellstrom2014-12-041-25/+17
| | | | | | | | | | | | | | | | * Coding style cleanups. * Use OS reserved trap 0x89 for IRQ Disable * Use OS reserved trap 0x8A for IRQ Enable * Add to SPARC CPU supplement documentation This will result in faster Disable/Enable code since the system trap handler does not need to decode which function the user wants. Besides the IRQ disable/enabled can now be inline which avoids the caller to take into account that o0-o7+g1-g4 registers are destroyed by trap handler. It was also possible to reduce the interrupt trap handler by five instructions due to this.
* score: PR2183: Fix context switch on SMPSebastian Huber2014-07-041-8/+49
| | | | | | | | Fix context switch on SMP for ARM, PowerPC and SPARC. Atomically test and set the is executing indicator of the heir context to ensure that at most one processor uses the heir context. Break the busy wait loop also due to heir updates.
* score: Fix CPU context usage on SMPSebastian Huber2014-05-081-3/+3
| | | | | | | | | | We must not alter the is executing indicator in _CPU_Context_Initialize() since this would cause an invalid state during a self restart. The is executing indicator must be valid at creation time since otherwise _Thread_Kill_zombies() uses an undefined value for not started threads. This could result in a system life lock.
* score: Implement forced thread migrationSebastian Huber2014-05-071-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of task migration in RTEMS has some implications with respect to the interrupt latency. It is crucial to preserve the system invariant that a task can execute on at most one processor in the system at a time. This is accomplished with a boolean indicator in the task context. The processor architecture specific low-level task context switch code will mark that a task context is no longer executing and waits that the heir context stopped execution before it restores the heir context and resumes execution of the heir task. So there is one point in time in which a processor is without a task. This is essential to avoid cyclic dependencies in case multiple tasks migrate at once. Otherwise some supervising entity is necessary to prevent life-locks. Such a global supervisor would lead to scalability problems so this approach is not used. Currently the thread dispatch is performed with interrupts disabled. So in case the heir task is currently executing on another processor then this prolongs the time of disabled interrupts since one processor has to wait for another processor to make progress. It is difficult to avoid this issue with the interrupt latency since interrupts normally store the context of the interrupted task on its stack. In case a task is marked as not executing we must not use its task stack to store such an interrupt context. We cannot use the heir stack before it stopped execution on another processor. So if we enable interrupts during this transition we have to provide an alternative task independent stack for this time frame. This issue needs further investigation.
* score: Statically initialize _ISR_Vector_tableSebastian Huber2014-04-291-1/+1
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* sparc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2014-04-281-48/+20
| | | | | | | | | | | | | | | | Use register g6 for the per-CPU control of the current processor. The register g6 is reserved for the operating system by the SPARC ABI. On Linux register g6 is used for a similar purpose with the same method since 1996. The register g6 must be initialized during system startup and then must remain unchanged. Since the per-CPU control is used in all critical sections of the operating system, this is a performance optimization for the operating system core procedures. An additional benefit is that the low-level context switch and interrupt processing code is now identical on non-SMP and SMP configurations.
* sparc: Optimize context switchSebastian Huber2014-04-281-4/+2
| | | | | | The registers g2 through g4 are reserved for applications. GCC uses them as volatile registers by default. So they are treated like volatile registers in RTEMS as well.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* sparc: Add support for interrupt profilingSebastian Huber2014-03-141-2/+23
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* bsps/sparc: Remove fix for ERC32 with FPU rev. B/CSebastian Huber2014-03-101-66/+0
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* sparc: Add LEON3_ASR17_PROCESSOR_INDEX_SHIFTSebastian Huber2014-02-141-1/+1
| | | | Add _LEON3_Get_current_processor().
* sparc: Save/restore only non-volatile contextSebastian Huber2014-02-121-15/+4
| | | | | | | | | | The _CPU_Context_switch() is a normal function call. The following registers are volatile (the caller must assume that the register contents are destroyed by the callee) according to "SYSTEM V APPLICATION BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0, o1, o2, o3, o4, o5. Drop these registers from the context. Ensure that offset defines match the structure offsets.
* score: _CPU_Context_switch_to_first_task_smp()Sebastian Huber2014-02-051-28/+0
| | | | | Delete _CPU_Context_switch_to_first_task_smp() and use _CPU_Context_restore() instead.
* bsps/sparc: Fix commentSebastian Huber2014-02-051-1/+1
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* bsps/sparc: Remove confusing nopSebastian Huber2014-02-041-1/+0
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* bsps/sparc: Order load/store by increasing offsetsSebastian Huber2014-02-041-7/+7
| | | | This may increase the cache hit performance.
* bsps/sparc: Fix commentsSebastian Huber2014-02-041-3/+1
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* sparc/shared/irq_asm.S: Get pointer to self per-CPU controlDaniel Hellstrom2013-11-301-0/+1
| | | | | | | | _CPU_Context_switch_to_first_task_smp() branches to done_flushing which requires o3 to be initalized with "self per-CPU control", this adds initialization of o3. This problem only affects SMP, see commit f8ad6c6f7f8b591e were usage of o3 was intruduced.
* sparc: Make _CPU_ISR_Dispatch_disable per-CPUSebastian Huber2013-08-091-22/+20
| | | | This variable must be available for each processor in the system.
* sparc: Move _CPU_Context_switch(), etc.Sebastian Huber2013-08-091-0/+224
| | | | | | Move the _CPU_Context_switch(), _CPU_Context_restore() and _CPU_Context_switch_to_first_task_smp() code since the method to obtain the processor index is BSP specific.
* bsps/sparc: SMP and per-CPU thread dispatch disableSebastian Huber2013-08-091-10/+25
| | | | Interrupt support for SMP and per-CPU thread dispatch disable level.
* bsps/sparc: Revert most SMP related changesSebastian Huber2013-08-091-111/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a side-effect the PR2082 is fixed with this and later changes. The commit restores the _ISR_Handler code to the original version in "cpukit/score/sparc/cpu_asm.S" in commit 6d42b4c60a4ac686489b793d5df2047c735c7c94. A list of reverted changes follows. commit c236082873cb4a2fd42af4ca0868106e1dd65422 Author: Sebastian Huber <sebastian.huber@embedded-brains.de> Date: Tue Jul 30 15:54:53 2013 +0200 smp: Provide cache optimized Per_CPU_Control Delete _Per_CPU_Information_p. This commit was completely reverted. commit e517714b7cd28807aad4c1afd8c97df72dadb4c1 Author: Jennifer Averett <jennifer.averett@oarcorp.com> Date: Tue Feb 26 12:31:23 2013 -0600 sparc: Remove dead code that was leftover from SMP development. This commit was completely reverted. commit 47a61aa16f81588f8ffb8ea5cfd1ceba3e9a867a Author: Joel Sherrill <joel.sherrill@OARcorp.com> Date: Fri Oct 7 14:35:03 2011 +0000 2011-10-07 Daniel Hellstrom <daniel@gaisler.com> PR 1933/cpukit * shared/irq_asm.S: From code inspection I have found the following issues (most SMP), and some improvements in irq_asm.S. I would need a long test with interrupts to verify the interrupt handler better, however I can not see that these patches hurt. Please see comment per hunk below, One should go through the file to indent delay-slots correctly, I have fixed some in the patch areas. An extra space is added in front of delay slots to indicate a delay slot. This commit was completely reverted. commit 0bd3f7e5d12fdbfb5bf4aa4a4169c67bfd92c988 Author: Jennifer Averett <Jennifer.Averett@OARcorp.com> Date: Thu Jul 28 17:33:07 2011 +0000 2011-07-28 Jennifer Averett <Jennifer.Averett@OARcorp.com> PR 1801 * shared/irq_asm.S: Modifications to synch the sparc with the smp working tree. This commit was completely reverted. commit 5d69cd33e9a72cf8c1a24fc9eda7f64d61f10fd1 Author: Joel Sherrill <joel.sherrill@OARcorp.com> Date: Wed Mar 16 20:05:30 2011 +0000 2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com> PR 1729/cpukit * shared/irq_asm.S: New file. The parts modifying the original code of _ISR_Handler were reverted. Only the content move remains.
* smp: Provide cache optimized Per_CPU_ControlSebastian Huber2013-07-311-11/+12
| | | | Delete _Per_CPU_Information_p.
* sparc: Remove dead code that was leftover from SMP development.Jennifer Averett2013-02-261-4/+0
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* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-111-2/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* 2011-10-07 Daniel Hellstrom <daniel@gaisler.com>Joel Sherrill2011-10-071-15/+6
| | | | | | | | | | | PR 1933/cpukit * shared/irq_asm.S: From code inspection I have found the following issues (most SMP), and some improvements in irq_asm.S. I would need a long test with interrupts to verify the interrupt handler better, however I can not see that these patches hurt. Please see comment per hunk below, One should go through the file to indent delay-slots correctly, I have fixed some in the patch areas. An extra space is added in front of delay slots to indicate a delay slot.
* 2011-07-28 Jennifer Averett <Jennifer.Averett@OARcorp.com>Jennifer Averett2011-07-281-64/+93
| | | | | | PR 1801 * shared/irq_asm.S: Modifications to synch the sparc with the smp working tree.
* 2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com>Joel Sherrill2011-03-161-0/+589
PR 1729/cpukit * shared/irq_asm.S: New file.
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