| Commit message (Collapse) | Author | Age | Files | Lines |
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The vector number of spurious interrupts was wrong after the interrupt
handler removal on SMP configurations.
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This is necessary to add tests that use the cache manager. For example
to get better estimates of worst-case timings.
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Since the per-CPU SMP lock must be acquired and released to send the
message a single interrupt broadcast operations offers no benefits. If
synchronization is required, then a SMP barrier must be used anyway.
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Rename bsp_smp_initialize() into _CPU_SMP_Initialize() since every CPU
port must supply this function.
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Merge RTEMS_FATAL_SOURCE_BSP_GENERIC and RTEMS_FATAL_SOURCE_BSP_SPECIFIC
into new fatal source RTEMS_FATAL_SOURCE_BSP. This makes it easier to
figure out the code position given a fatal source and code.
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Instead of SPRG0 (= special purpose register 272) use the new global
symbol _PPC_INTERRUPT_DISABLE_MASK to store the interrupt disable mask.
The benefit is that it is now possible to disable interrupts without
further run-time initialization in boot_card().
At least on Freescale e500 cores this leads also to a faster execution
since the mfmsr and mfspr instruction require four cycles to complete.
The instructions to load the mask value can execute while the mfmsr is
in progress.
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Add a CPU counter interface to allow access to a free-running counter.
It is useful to measure short time intervals. This can be used for
example to enable profiling of critical low-level functions.
Add two busy wait functions rtems_counter_delay_ticks() and
rtems_counter_delay_nanoseconds() implemented via the CPU counter.
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The readv() and writev() support was implemented in terms of multiple
calls to the read and write handlers. This imposes a problem on device
files which use an IO vector as single request entity. For example a
low-level network device (e.g. BPF(4)) may use an IO vector to create
one frame from multiple protocol layers each with its own IO vector
entry.
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This patch refactors a lot of the existing doxygen within libbsp/arm/lpc32xx.
Much of this refactoring was just renaming of existing groups to conform to a
more consistent naming structure. With the addition of a doxygen header for
tm27.h, all files within lpc32xx belong to doxygen group now. lpc32xx should
be used a reference for adding doxygen to other bsps.
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Add support for MMU initialization for RaspberryPi. Introduce new shared
MMU configuration table that can be used by other BSPs that call the
arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache function.
Demonstrate the use of the generic table with RaspberryPi.
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pc386 set CLOCK_DRIVER_ISRS_PER_TICK to a
string rather than a numeric value. Add
CLOCK_DRIVER_ISRS_PER_TICK_VALUE and
other clean up on the clock driver.
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Use the value rather than being defined. This allows inverted
logic to be used.
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Move implementation specific parts of object.h and object.inl into new
header file objectimpl.h. The object.h contains now only the
application visible API.
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Delete bsp_smp_interrupt_cpu().
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Add and use _SMP_Get_current_processor() and
rtems_smp_get_current_processor().
Delete bsp_smp_interrupt_cpu().
Change type of current processor index from int to uint32_t to match
_SMP_Processor_count type.
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Use bspreset_loop.c instead. This avoids infinite recursion.
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Add bsp_generic_fatal().
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This field is unused except for special case simulator clock drivers.
In these places use an alternative. Add and use
_Thread_Set_global_exit_status() and _Thread_Get_global_exit_status().
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Eliminate copy and paste. Use the _Objects_Information_table since this
will take into account that more than one internal thread may exist,
e.g. MPCI thread or idle threads of secondary processors.
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Delete bsp_smp_wait_for(). Other parts of the system work without
timeout, e.g. the spinlocks. Using a timeout here does not make the
system more robust.
Delete bsp_smp_cpu_state and replace it with Per_CPU_State. The
Per_CPU_State follows the Score naming conventions. Add
_Per_CPU_Change_state() and _Per_CPU_Wait_for_state() functions to
change and observe states.
Use Per_CPU_State in Per_CPU_Control instead of the anonymous integer.
Add _CPU_Processor_event_broadcast() and _CPU_Processor_event_receive()
functions provided by the CPU port. Use these functions in
_Per_CPU_Change_state() and _Per_CPU_Wait_for_state().
Add prototype for _SMP_Send_message().
Delete RTEMS_BSP_SMP_FIRST_TASK message. The first context switch is
now performed in rtems_smp_secondary_cpu_initialize(). Issuing the
first context switch in the context of the inter-processor interrupt is
not possible on systems with a modern interrupt controller. Such an
interrupt controler usually requires a handshake protocol with interrupt
acknowledge and end of interrupt signals. A direct context switch in an
interrupt handler circumvents the interrupt processing epilogue and may
leave the system in an inconsistent state.
Release lock in rtems_smp_process_interrupt() even if no message was
delivered. This prevents deadlock of the system.
Simplify and format _SMP_Send_message(),
_SMP_Request_other_cores_to_perform_first_context_switch(),
_SMP_Request_other_cores_to_dispatch() and
_SMP_Request_other_cores_to_shutdown().
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Do not call bsp_smp_secondary_cpu_initialize() in
rtems_smp_secondary_cpu_initialize(). This allows more flexibilty in
the BSP low-level code. Specify context requirements for a call to
rtems_smp_secondary_cpu_initialize().
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Call _SMP_Handler_initialize() later and move bsp_smp_initialize() into
_SMP_Handler_initialize(). Change bsp_smp_initialize() prototype to
match integer types of calling context.
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Rename open_dev_console() to rtems_libio_post_driver(). Rename
rtems_libio_supp_helper to rtems_libio_post_driver_helper.
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