Commit message (Collapse) | Author | Age | Files | Lines | |
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* | bsp/riscv: Remove bogus Automake conditional | Sebastian Huber | 2019-11-14 | 1 | -7/+0 |
| | | | | Update #3785. | ||||
* | riscv: Address differences in the linkerscript between GNU LD and LLVM/LLD | Hesham Almatary | 2019-10-27 | 1 | -0/+13 |
| | | | | | | | | | | LLVM/LLD does not support STARTUP and ALIGN_WITH_INPUT directives that GNU LD support. INPUT and ALIGN(8) are supported by LLVM/LLD and can replace the unsupported STARTUP/ALIGN_WITH_INPUT directives. The commit conditionally adds the supported directive that linkers can understand depending on the toolchain used to compile RTEMS i.e., clang or gcc. Clang is assumed to use LLD by default. | ||||
* | riscv: Generate linkcmds.base from the shared linkcmds.base.in | Hesham Almatary | 2019-10-27 | 2 | -1/+2 |
| | | | | | This commit moves the existing linkcmds.base to linkcmds.base.in in order to make it configurable by autotools. | ||||
* | riscv: add freedom E310 Arty A7 bsp | Pragnesh Patel | 2019-10-23 | 2 | -1/+23 |
| | | | | | | | Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board. Update #3785. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> | ||||
* | riscv: add griscv bsp | Jiri Gaisler | 2019-01-22 | 1 | -2/+2 |
| | | | | Update #3678. | ||||
* | build: Remove local.am | Sebastian Huber | 2018-10-10 | 1 | -1/+0 |
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* | bsp/riscv: Use CPU counter btimer | Sebastian Huber | 2018-07-25 | 1 | -1/+1 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Add basic SMP startup | Sebastian Huber | 2018-07-25 | 1 | -1/+1 |
| | | | | Update #3433. | ||||
* | bsps/riscv: Update linker-symbols.h | Sebastian Huber | 2018-07-25 | 1 | -1/+0 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Disable HTIF support by default | Sebastian Huber | 2018-07-25 | 1 | -2/+2 |
| | | | | | | The HTIF is a legacy machinery. Update #3433. | ||||
* | riscv: Rework exception handling | Sebastian Huber | 2018-07-25 | 2 | -1/+4 |
| | | | | | | | | | | | Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433. | ||||
* | bsp/riscv: Add console support for NS16550 devices | Sebastian Huber | 2018-07-06 | 1 | -0/+6 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Add device tree support for console | Sebastian Huber | 2018-06-28 | 2 | -5/+7 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Add device tree support | Sebastian Huber | 2018-06-28 | 2 | -0/+13 |
| | | | | Update #3433. | ||||
* | riscv: Add dummy SMP support | Sebastian Huber | 2018-06-28 | 1 | -0/+3 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Add BSP options to define RAM region | Sebastian Huber | 2018-06-27 | 1 | -2/+24 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Remove unused BSP options | Sebastian Huber | 2018-06-27 | 1 | -10/+0 |
| | | | | Update #3433. | ||||
* | bsp/riscv_generic: Rename to "riscv" | Sebastian Huber | 2018-06-27 | 2 | -0/+100 |
Update #3433. |