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* Fixed bug where the last link of the RDA was not initialized properly.Joel Sherrill1998-08-121-15/+30
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* Added SONIC_DEBUG_DESCRIPTORS and changed debug level.Joel Sherrill1998-08-111-3/+11
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* Survives 16-20 packets. Appears to be ok on TX buffer management.Joel Sherrill1998-08-101-11/+16
| | | | Problem appears to be on the RX buffer initialization side.
* Added printsJoel Sherrill1998-08-101-1/+2
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* Can now reply to multiple successive pings successfully without being inJoel Sherrill1998-08-102-29/+22
| | | | | | promiscuous mode. It still dies somewhere between 16 and 20 pings.
* replies to ping -- forced into prosmiscuous modeJoel Sherrill1998-08-101-13/+21
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* Reordered some stuff.Joel Sherrill1998-08-081-7/+10
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* Changed debug level.Joel Sherrill1998-08-082-36/+96
| | | | | | | | | | | | | | | | Moved CAM Descriptor types to sonic.h. CAM memory is now malloced to insure it shares the same upper address bits. Removed increment of RX interrupt count on TX interrupt path. Added SONIC_DEBUG_FRAGMENTS and SONIC_DEBUG_CAM conditionals. Fixed bugs in fragment manipulation. First bug was that the pad overwrote the last fragment. The second bug was that the link information overwrote the size of the last fragment. Rewrote initialization of TDA to simplify it.
* Removed SonicRegisters structure since we now use register indicesJoel Sherrill1998-08-061-83/+15
| | | | | | | | and access routines. Added revision constants. Added in_use and EOL field values.
* Enabled specific types of debug info.Joel Sherrill1998-08-061-31/+55
| | | | | | | | | | | | Added pointer to RDA to sonic structure. Added macro names for values used in the in_use field of RDA entries. Rewrote the RX Descriptor Area initialization loop. Added a check to barf if this is a Rev B sonic chip. Enabled check that the CAM was properly loaded.
* Changed debug enable macros to support individually enabling differentJoel Sherrill1998-08-061-15/+30
| | | | | | | types of debug information. Removed call to rtems_panic which was based on checking a variable which was no longer being set.
* Card Resource Register was a 16-bit register not a 32-bit one.Joel Sherrill1998-08-065-28/+36
| | | | Used existing constants for bits on the register.
* Added support for the Card Resource Register. The new probe routinesJoel Sherrill1998-08-065-8/+107
| | | | | check for the presence of the DUART, SCC, and RTC. The SONIC check needs to be added in the future as the network driver is libchip'ed.
* Added constants which made the multiple bit settings more readableJoel Sherrill1998-08-051-0/+25
| | | | for the Data Configuration Register (DCR).
* DCR setting changed to match what the DY-4 Firmware initialized it to.Joel Sherrill1998-08-051-135/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This primarily included setting the state of the programmable outputs and the RX and TX FIFO depths. Moved all of the TX, RX, and RRA data structure initialization to before the hardware initialization. As part of this, the hardware initialization was consolidated. More than likely, some of this movement broke stuff. Used constants added to sonic.h which gave more logical names to some of the register bit settings. Switched to calloc to insure the data areas where initialized to 0. Commented out a panic check in the RX server which may or may not have been right. Increased the size of the CAM initialization area. It is possible that this could be decreased or code added to handle the management of multiple hardware addresses. Added sonic read and write register routines which aid greatly in debugging and provide the core for the eventual movement of this driver to libchip. Added debug code to the read and write register routines which can print the value read from or written to a register. This code also prints the register name which significantly eases reading the log.
* Switched to read/write register routines and added some basic debugJoel Sherrill1998-08-032-332/+473
| | | | help.
* Changed name of network driver.Joel Sherrill1998-07-301-1/+1
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* Added temporary include of dmv170.hJoel Sherrill1998-07-301-0/+6
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* Added SONIC configuration information.Joel Sherrill1998-07-301-0/+9
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* Added a hint to continue writing this.Joel Sherrill1998-07-301-0/+2
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* Changed clock rate from 32 Khz to 1 Mhz.Joel Sherrill1998-07-302-6/+6
| | | | Registers are at 8 byte boundaries NOT 4 as initially configured.
* Changed comment to be more polite.Joel Sherrill1998-07-301-1/+1
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* Updating to make more readable.Joel Sherrill1998-07-301-28/+8
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* Spacing corrected.Joel Sherrill1998-07-301-1/+0
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* New file based on email from DY-4 technical support.Joel Sherrill1998-07-301-0/+62
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* Fixed spacing.Joel Sherrill1998-07-301-1/+0
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* Updated to accurately reflect the dmv177.Joel Sherrill1998-07-301-22/+21
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* Made chain.h sharedJoel Sherrill1998-07-302-355/+1
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* Made tod.h sharedJoel Sherrill1998-07-302-39/+2
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* Added reference to shared TOD driver.Joel Sherrill1998-07-291-1/+1
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* Corrected to reflect the ICM7170 which is really on this board.Joel Sherrill1998-07-292-16/+12
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* Added config.c and deleted tod.c.Joel Sherrill1998-07-291-1/+1
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* Simplified RTC base address.Joel Sherrill1998-07-291-2/+1
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* Changed cast on RTC address and added base address of RTC fields as opposedJoel Sherrill1998-07-291-1/+2
| | | | to entire RTC with NVRAM included.
* First cut at configuration table for libchip RTC. At this point, weJoel Sherrill1998-07-284-275/+117
| | | | are pretending that the DMV177 has an M48T08.
* Removed "if 0" used to switch between serial ports.Joel Sherrill1998-07-252-4/+0
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* Moved console.c to libbsp/shared.Joel Sherrill1998-07-252-291/+1
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* Changed so we could test interrupts on port 3.Joel Sherrill1998-07-182-4/+4
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* Removed use of data port for z8530.Joel Sherrill1998-07-182-14/+14
| | | | | Tested all four ports. MC68681 as both polled and interrupt. Z8530 as polled only.
* New fileJoel Sherrill1998-07-181-0/+62
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* Added z85c30 specific probe routine to decide what the clock rate was.Joel Sherrill1998-07-182-8/+52
| | | | | | This routines could be enhanced to determine if the SCC is present since it appears from the DY-4 manual that a status registers indicates this.
* Addresses for SCC were wrong. A and B ports were swapped.Joel Sherrill1998-07-181-44/+25
| | | | | | | Deleted CSS interface related items. Added items required to access DMA Control and Status Register so we could figure out dynamically what the clock speed of the SCC really is.
* Swapped RX and TX since doing this makes the lights blink on theJoel Sherrill1998-07-181-2/+2
| | | | | | | RS-422 converter. We now see the TD light blink when typing characters in HyperTerminal and when the board is reset we see the RD light blink. This leads us to believe the cabling is basically right.
* Added RS-422 converter information and cable building information.Joel Sherrill1998-07-181-8/+59
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* Added information on the MC68681.Joel Sherrill1998-07-181-2/+12
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* Added background and setup to add section on RS-422.Joel Sherrill1998-07-181-11/+21
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* Reworked to removed dependency on DY-4 CSS ROM monitor interface.Joel Sherrill1998-07-181-5/+2
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* Removed css_iface.Joel Sherrill1998-07-182-2/+2
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* Removed. We are no longer dependent on DY-4 CSS interface code.Joel Sherrill1998-07-182-216/+0
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* New file.Joel Sherrill1998-07-181-0/+26
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