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* Regenerate all preinstall.am files.Joel Sherrill2014-08-2816-86/+86
| | | | | Apparently, at some point automake output changed and these were not updated.
* arm: Add tests which fail to build with C++ enabled.Chris Johns2014-08-289-0/+24
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* preinstall: Regenerated files differ from the repo.Chris Johns2014-08-281-6/+6
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* nds/Makefile.am: Rework to avoid creating ltos of .rel filesJoel Sherrill2014-08-271-71/+35
| | | | This was necessary to enable all tests to link.
* lpc40xx_ea_rom_int-testsuite.tcfg: New fileJoel Sherrill2014-08-271-0/+7
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* arm/lm3s3749: Add tests that do not fit.Chris Johns2014-08-271-0/+3
| | | | You need --enable-c++ for the c++ tests.
* bsp/altera-cyclone-v: Add DMA support hwlib filesSebastian Huber2014-08-2617-7/+21297
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* bsp/altera-cyclone-v: Update to hwlib 13.1Sebastian Huber2014-08-2616-3841/+8786
| | | | This version is distributed with SoC EDS 14.0.0.200.
* bsp/tms570: implemented and tested initialization of Cortex-R performance ↵Pavel Pisa2014-08-221-4/+84
| | | | | | | | | | | | counters. The code is written as BSP specific now but it should work for all Cortex-A and R based CPUs and can be moved to ARM generic place in future. StackOverflow suggested sequences of writes to the registers required to start counters is used. http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor
* libchip/dwmac: Make PHY address user configurableChristian Mauderer2014-08-221-0/+28
| | | | | | This patch allows the user to configure the PHY address for the DWMAC driver by giving a pointer to a dwmac_user_cfg structure to network stack via rtems_bsdnet_ifconfig::drv_ctrl.
* bsp/tms570: disable huge memory demanding tests for internal RAM build variant.Pavel Pisa2014-08-212-13/+23
| | | | | | | | | | | | | BSP completes build with tests and debug enabled for all three variants now tms570ls3137_hdk tms570ls3137_hdk_intram tms570ls3137_hdk_sdram Even that all enabled tests builds for internal RAM variant, many of them are expected to fail on hardware because whole tests including code, data and runtime work area demands has to fit into 256 kB of RAM.
* bsp/tms570: implemented support functions to satisfy complete tests build ↵Pavel Pisa2014-08-219-4/+186
| | | | | | | | requirements. This patch enables to build all RTEMS tests for tms570ls3137_hdk_sdram BSP variant in in default build. Debug build with --enable-rtems-debug set has succeed for samples subset of tests as well.
* libbsp/arm/acinclude.m4: Regenerate for tms570Joel Sherrill2014-08-201-0/+2
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* BSP for TMS570LS31x Hercules Development Kit from TI (TMS570LS3137)Premysl Houdek2014-08-2028-0/+2389
| | | | | | | | | | | | | | | | | | | | | | | | | Included variants: tms570ls3137_hdk_intram - place code and data into internal SRAM tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM tms570ls3137_hdk - variant prepared for stand-alone RTEMS aplication stored and running directly from flash. Not working yet. Chip initialization code not included in BSP. External startup generated by TI's HalCoGen was used for testing and debugging. More information about TMS570 BSP can be found at http://www.rtems.org/wiki/index.php/Tms570 Patch version 2 - most of the formatting suggestion applied. - BSP converted to use clock shell - console driver "set attributes" tested. Baudrate change working Patch version 3 - more formatting changes. - removed leftover defines and test functions Todo: refactor header files (name register fields)
* lpc24xx/lpc17xx: lpc24xx_pin_set_function() keep LPC4088 W type pin in ↵Pavel Pisa2014-08-201-1/+6
| | | | | | | | | | | | | | | | | | | | digital mode for non-analog function. The problem wit incorrect switching of pins into analog mode manifestes on LPC4088 based board. LPC4088 implements pin P1.17 (ENET_MDIO) as new W type (digital pin with analog option). The pin was listed as D category on LPC1788 which does not have analog mode control bit. If analog option is not explicitly switched off on LPC4088 then the pin does not work as digital pin. Code tested on LPC1788 and no problems has been observed even that manual specifies the IOCON_ADMODE field as reserved and should be written as zero. But even RTEMS lpc24xx_gpio_config sets this bit unconditionally. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* bsp/lpc24xx: Add LPC40XX variantsSebastian Huber2014-08-128-19/+99
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* arm: Add support for FPv4-SP floating point unitSebastian Huber2014-08-121-0/+15
| | | | | This floating point unit is available in Cortex-M4 processors and defined by ARMv7-M. This adds basic support for other VFP-D16 variants.
* bsp/altera-cyclone-v: Add RTC driver.Christian Mauderer2014-08-114-4/+381
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* bsp/altera-cyclone-v: Add a simple I2C driver.Christian Mauderer2014-08-1111-7/+10389
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* bsp/altera-cyclone-v: Add socal from hwlib.Christian Mauderer2014-08-112-2/+60
| | | | Some of the headers from the hwlib need the files from the socal subdirectory.
* Add More Testsuite Configuration Files and Update Existing OnesJoel Sherrill2014-07-169-0/+53
| | | | | | | The first pass at building these was without networking enabled. This pass addresses that plus accounts for some new BSPs which needed testsuite.tcfg files and BSPs which could not link tests which had been added since the first pass.
* Common ARM A8 code.Chris Johns2014-07-161-0/+55
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* bsp/altera-cyclone-v: Move MMU configuration tableSebastian Huber2014-07-013-20/+37
| | | | This makes it possible to use application specific version.
* bsps/arm: Rename bsp_mm_config_tableSebastian Huber2014-07-013-11/+9
| | | | | | Rename bsp_mm_config_table to arm_cp15_start_mmu_config_table and rename bsp_mm_config_table_size to arm_cp15_start_mmu_config_table_size to be in line with the other names in <bsp/arm-cp15-start.h>.
* bsp/realview-pbx-a9: Fix SMP startupSebastian Huber2014-06-121-0/+14
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* lm3s6965-testsuite.cfg: Add pppd.Martin Galvan2014-06-101-0/+1
| | | | | | When trying to compile RTEMS for the Stellaris LM3S6965 board, I had an issue of pppd.exe's .rodata section being too big to fit in the board's memory image (region 'ROM_INT' overflowed).
* bsp/lpc176x: New BSPMartin Boretto2014-06-1042-0/+6504
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* bsps/arm: Fix Cortex-A9 MPCore clock driverSebastian Huber2014-06-061-9/+18
| | | | | | The nanoseconds extension returned wrong values on secondary processors since some of the global timer registeres are banked. Use global variables instead.
* bsp/altera-cyclone-v: Enable unified L2 cacheSebastian Huber2014-06-062-1/+12
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* bsp/altera-cyclone-v: Move SMP supportSebastian Huber2014-06-063-54/+94
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* bsps/arm: Change L2 cache initializationSebastian Huber2014-06-062-50/+1
| | | | | Do not touch the L1 caches since they have been initialized by the start hooks.
* bsp/altera-cyclone-v: Simplify start hooksSebastian Huber2014-06-061-120/+25
| | | | Use arm_a9mpcore_start_hook_0(). The L2 cache is now disabled.
* bsp/altera-cyclone-v: Change default baudSebastian Huber2014-06-061-1/+1
| | | | Use value for standard U-Boot.
* bsp/altera-cyclone-v: Use NOLOAD for nocache secSebastian Huber2014-06-061-1/+1
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* bsp/altera-cyclone-v: Simplify MMU config tableSebastian Huber2014-06-061-2/+1
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* bsps/arm: Define ARM_CP15_TEXT_SECTIONSebastian Huber2014-06-069-44/+18
| | | | | Define ARM_CP15_TEXT_SECTION to BSP_START_TEXT_SECTION so that the start code is in the right section.
* bsps/arm: Simplify L1 caches supportSebastian Huber2014-06-051-55/+12
| | | | Delete superfluous/incorrect interrupt disable/enable.
* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-0/+5
| | | | Invalidate entire branch predictor array.
* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-4/+4
| | | | Enable SCU only on the boot processor.
* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-6/+13
| | | | Add arm_a9mpcore_start_enable_smp_in_auxiliary_control().
* bsps/arm: Simplify Cortex-A9 MPCore startSebastian Huber2014-06-051-31/+32
| | | | | Add arm_a9mpcore_start_on_secondary_processor(). Rely on error checks in _SMP_Start_multitasking_on_secondary_processor().
* bsps/gdbarmsim: Add the missing bspstarthooks.c.Chris Johns2014-05-301-0/+20
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* bsps: Do not build tests that require a tick interrupt.Chris Johns2014-05-285-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following BSPs do not have tick support so the tests fail: arm1136jfs arm1136js arm7tdmi arm920 armcortexa9 (does not run any more) avrtest h8sim h8sxsim m32csim m32rsim moxiesim simsh1 simsh2 simsh4 v850e1sim v850e2sim v850e2v3sim v850esim v850essim v850sim This list was provided by Joel in the following post: http://www.rtems.org/pipermail/rtems-devel/2014-April/006526.html
* bsp/altera-cyclone-v: CleanupRalf Kirchner2014-05-281-3/+3
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* bsp/altera-cyclone-v: Reduce size of nocache heapRalf Kirchner2014-05-282-4/+4
| | | | Network mbufs and clusters now are cached. Thus the nocache heap can get reduced to 1 MByte.
* bsp/altera-cyclone-v: Cache mbufs and clustersRalf Kirchner2014-05-281-12/+0
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* bsp/altera-cyclone-v: Enable L2 cache for network driverRalf Kirchner2014-05-281-1/+14
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* bsp/altera-vyclone-v: Broadcast cache maintenancesRalf Kirchner2014-05-281-3/+3
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* bsp/arm: Broadcast cache maintenancesRalf Kirchner2014-05-281-1/+1
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* bsp/gdbarmsim: Switch to the standard arm/shared/startup.Chris Johns2014-05-265-402/+143
| | | | | | | Switch to the standard ARM startup code. This requires adding the standard interrupt code. The interrupt code does nothing at this point in time. I do not know if the ARM simulator in GDB supports interrupts.
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