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* bsps: Fix TLS support in linker command filesSebastian Huber2014-04-222-2/+6
| | | | | The TLS section symbols had wrong values in case of an empty TLS data section and a nonempty TLS BSS section.
* bsp/arm: Cleanup L2 cache handlingRalf Kirchner2014-04-171-38/+7
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* bsp/arm: Correct L2 cache enable methodRalf Kirchner2014-04-171-53/+48
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* bsp/arm: Add cache size methodsRalf Kirchner2014-04-172-0/+115
| | | | Add new methods which deliver the cache sizes of for supported cache levels.
* bsp/arm: Add L2 cache lockingRalf Kirchner2014-04-171-9/+34
| | | | This level 2 cache is a shared data and instruction cache and thus needs locking.
* bsp/arm: Remove unused cache store methodsRalf Kirchner2014-04-172-30/+0
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* bsp/arm: Correct cache misalignment handlingRalf Kirchner2014-04-172-32/+60
| | | | Correct misalignment handling and prepare for locking.
* bsp/arm: Correct L2 cache flushingRalf Kirchner2014-04-171-17/+31
| | | | Correct misalignment handling and prepare for locking.
* bsp/arm: Remove arm erratum 764369 from L2 cacheRalf Kirchner2014-04-171-14/+0
| | | | Arm erratum 764369 only applies to the level 1 cache.
* bsp/arm: Consistenly same handling for flushingRalf Kirchner2014-04-171-2/+2
| | | | | It is importeant to consistently apply the same handling for flushing within level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
* bsp/arm: RTEMS_SMP to arm erratum 764369 detectionRalf Kirchner2014-04-173-10/+8
| | | | Move the RTEMS_SMP conditional compilation to the detection method of arm erratum 764369
* bsp/arm: Erratum 764369 after enabling SCURalf Kirchner2014-04-171-1/+1
| | | | Execute the SCU part of the workaround of arm erratum 764368 after the SCU was enabled.
* bsp/arm: Correct detection of arm erratum 764368Ralf Kirchner2014-04-171-0/+1
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* bsp/arm: Cleanup L1 cacheRalf Kirchner2014-04-171-2/+2
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* bsp/altera-cyclone-v: CleanupRalf Kirchner2014-04-171-2/+0
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* bsp/altera-cyclone-v: Change console baud rateRalf Kirchner2014-04-171-1/+1
| | | | | | The baud rate of the altera cyclone-V U-Boot can not be changed at the u-Boot console prompt. Thus we use the same baud rate as the U-Boot for the BSP.
* score: SMP initialization changesSebastian Huber2014-04-141-15/+26
| | | | | | | | | | | | | | | | | Add and use _CPU_SMP_Start_processor(). Add and use _CPU_SMP_Finalize_initialization(). This makes most _CPU_SMP_Initialize() functions a bit simpler since we can calculate the minimum value of the count of processors requested by the application configuration and the count of physically or virtually available processors in the high-level code. The CPU port has now the ability to signal a processor start failure. With the support for clustered/partitioned scheduling the presence of particular processors can be configured to be optional or mandatory. There will be a fatal error only in case mandatory processors are not present. The CPU port may use a timeout to monitor the start of a processor.
* rtems: Rename rtems_smp_get_current_processor()Sebastian Huber2014-04-111-1/+1
| | | | | | | Rename rtems_smp_get_current_processor() in rtems_get_current_processor(). Make rtems_get_current_processor() a function in uni-processor configurations to enable ABI compatibility with SMP configurations.
* gba/include/bsp.h: Remove rtems_bsp_delay()Joel Sherrill2014-03-211-12/+0
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* Change all references of rtems.com to rtems.org.Chris Johns2014-03-21289-289/+289
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* bsps/arm: Add DP83848 PHY support to LPC EthernetPavel Pisa2014-03-141-0/+8
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* bsps/arm: Add PHY detection to LPC EthernetPavel Pisa2014-03-141-13/+45
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* bsps/arm: Reset MII management in LPC EthernetPavel Pisa2014-03-141-1/+7
| | | | Reduce MII clock to support LPC17XX.
* bsp/lpc24xx: Add LPC24XX_PIN_ETHERNET_POWER_DOWNPavel Pisa2014-03-142-0/+15
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* bsp/lpc24xx: Add lpc24xx_pin_get_first_index()Sebastian Huber2014-03-141-0/+10
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* bsp/altera-cyclone-v: Made hwlib compile cleanRalf Kirchner2014-03-133-281/+6
| | | | Made Alteras hwlib compile clean within the RTEMS build system
* bsp/altera-cyclone-v: Add Alteras hwlibRalf Kirchner2014-03-1323-0/+71250
| | | | Add files from Alteras hwlib
* bsp/altera-cyclone-v: New BSPRalf Kirchner2014-03-1322-0/+2544
| | | | | | | | | | | | | Implemented so far: - nocache heap for uncached RAM - basic timer - level 1 cache handling for arm cache controller in arm-cache-l1.h - level 2 L2C-310 cache controller - MMU - DWMAC 1000 ethernet controller - basic errata handling - smp startup for second core
* libbsp/xilinx-zynq: Share handling for ARM cache controller L2C-310Ralf Kirchner2014-03-133-988/+4
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* bsp/arm: Add handling for level 2 L2C-310 cache controllerRalf Kirchner2014-03-132-0/+1998
| | | | | | arm-l2c-310/cache_.h contains the handling for the L2C-310 level 2 cache controller from arm. It references the arm level 1 cache handling in the new file arm-cache-l1.h.
* bsp/arm: Add SCU errata handling for L2C-310 cacheRalf Kirchner2014-03-132-10/+36
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* bsp/xilinx-zynq: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+10
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* bsp/realview-pbx-a9: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+10
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* bsp/raspberrypi: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+10
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* bsp/lpc32xx: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+10
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* bsp/arm: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+279
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* bsp/arm: Add linker symbol bsp_processor_countRalf Kirchner2014-03-131-0/+2
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* bsp/arm: Separate setup for translation tableRalf Kirchner2014-03-131-4/+20
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* bsp/arm: Invalidate SCURalf Kirchner2014-03-132-1/+25
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* bsp/arm: SMP support for a9mpcore_clock_cleanup()Ralf Kirchner2014-03-131-4/+18
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* bsp/arm: Avoid warningRalf Kirchner2014-03-131-0/+1
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* bsps: Add empty cache managerSebastian Huber2014-02-2410-0/+51
| | | | | This is necessary to add tests that use the cache manager. For example to get better estimates of worst-case timings.
* score: Rename rtems_smp_process_interrupt()Sebastian Huber2014-02-192-5/+4
| | | | | | Rename rtems_smp_process_interrupt() into _SMP_Inter_processor_interrupt_handler(). Delete unused header file <rtems/bspsmp.h>.
* score: Rename rtems_smp_secondary_cpu_initialize()Sebastian Huber2014-02-191-1/+2
| | | | | | Rename rtems_smp_secondary_cpu_initialize() into _SMP_Start_multitasking_on_secondary_processor(). Move declaration to <rtems/score/smpimpl.h>.
* score: Delete bsp_smp_broadcast_interrupt()Sebastian Huber2014-02-191-12/+0
| | | | | | Since the per-CPU SMP lock must be acquired and released to send the message a single interrupt broadcast operations offers no benefits. If synchronization is required, then a SMP barrier must be used anyway.
* score: Rename bsp_smp_initialize()Sebastian Huber2014-02-191-1/+1
| | | | | Rename bsp_smp_initialize() into _CPU_SMP_Initialize() since every CPU port must supply this function.
* score: Add RTEMS_FATAL_SOURCE_BSPSebastian Huber2014-02-198-70/+12
| | | | | | Merge RTEMS_FATAL_SOURCE_BSP_GENERIC and RTEMS_FATAL_SOURCE_BSP_SPECIFIC into new fatal source RTEMS_FATAL_SOURCE_BSP. This makes it easier to figure out the code position given a fatal source and code.
* score: Add CPU counter supportSebastian Huber2014-02-1420-5/+60
| | | | | | | | | Add a CPU counter interface to allow access to a free-running counter. It is useful to measure short time intervals. This can be used for example to enable profiling of critical low-level functions. Add two busy wait functions rtems_counter_delay_ticks() and rtems_counter_delay_nanoseconds() implemented via the CPU counter.
* bsps/arm: Fix Cortex-A9 MPCore nanoseconds handlerSebastian Huber2014-02-131-1/+1
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* bsps/arm: Use Global Timer for Cortex-A9 MPCoreSebastian Huber2014-02-105-29/+78
| | | | | | Use the Global Timer for the Cortex-A9 MPCore clock driver instead of the Private Timer. This enables a consistent nanoseconds since last context switch value across all processors.
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