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* arm/lpc176x/make/custom/lpc1768_mbed-testsuite.tcfg: Add tmfine01Joel Sherrill2015-03-171-0/+1
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* arm/lm3s69xx/make/custom/lm4f120-testsuite.tcfg: Add tmfine01Joel Sherrill2015-03-171-0/+1
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* preliminary Raspberry Pi Model 2 supportAlan Cudmore2015-03-166-22/+55
| | | | | | | | | | | | | | | | | This patch adds a BSP variant for the Raspberry Pi 2. You can build both variants by configuring with the option --enable-rtemsbsp="raspberrypi2 raspberrypi" For the current BSP, the only change was the peripheral register base address and the compiler options. The raspberrypi/make/custom rules were re-factored: raspberrypi.inc -- Common rules raspberrypi.cfg -- Raspberry Pi 1 specific rule/optons raspberrypi2.cfg -- Raspberry Pi 2 specific rule/options I tested hello, ticker, unlimited, and paranoia on both the Pi (Model A+) and Pi 2.
* beagle bsp: delete TIMER_FREQ, TIMER_COUNTBen Gras2015-03-141-4/+0
| | | | | | unused and poorly named (no prefix) and colliding with sp68. Closes #2302.
* rtl22xx.cfg: Remove -DNDEBUG flagJoel Sherrill2015-03-091-1/+1
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* lpc1768_mbed.cfg: Remove -DNDEBUG flagJoel Sherrill2015-03-091-1/+1
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* Add fsscandir01 variants as needed to more BSPs testsuite configurationJoel Sherrill2015-03-0612-0/+15
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* raspberrypi: Do not include default IRQ handler and BSP specific oneJoel Sherrill2015-03-061-1/+0
| | | | | | This was tripping a linker error in the dl0[12] tests. closes 2247.
* lpc1768_mbed_ahb_ram-testsuite.tcfg: Add ftp01Joel Sherrill2015-03-061-0/+1
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* lpc1768_mbed_ahb_ram.tcfg: Remove as it is a junk fileJoel Sherrill2015-03-061-7/+0
| | | | | This file does not have "-testsuite" in the name and is ignored by the build system.
* Fix a number of minor Doxygen formatting issuesJoel Sherrill2015-03-061-1/+1
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* ARM: Add BSP_START_NEEDS_REGISTER_INITIALIZATIONMartin Galvan2015-02-274-0/+139
| | | | | | | | | | | | | This patch adds the macro BSP_START_NEEDS_REGISTER_INITIALIZATION and three hooks for BSP-specific register init code to arm/shared/start.S. Said hooks are bsp_start_init_registers_core (intended for initializing the ARM core registers), bsp_start_init_registers_banked_fiq (for the FIQ mode banked registers) and bsp_start_init_registers_vfp (for the FPU registers). BSP_START_NEEDS_REGISTER_INITIALIZATION would be defined in a BSP's configure.ac (so that it appears in its bspopts.h). This patch also adds the register init code required by the TMS570. We've tested it with the tms570ls3137_hdk.cfg config and it works fine.
* ARM: Support VFP-D16Martin Galvan2015-02-201-3/+5
| | | | | | | | | This patch allows the existing FPU code to support both VFP-D16 and VFP-D32. According to ARM, writes to D32DIS are ignored for D16 so there's no need to enclose the bic instruction with an #ifdef. We tested it on a TMS570LS3137 using TI initialization code and it works fine. Signed-off by: Martin Galvan <martin.galvan@tallertechnologies.com>
* score: Add _CPU_SMP_Prepare_start_multitasking()Sebastian Huber2015-02-171-0/+5
| | | | Update #2268.
* lpc1768_mbed_ahb_ram_eth-testsuite.tcfg: Add ftp01Joel Sherrill2015-02-131-0/+1
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* lpc1768_mbed-testsuite.tcfg: Add ftp01Joel Sherrill2015-02-131-0/+1
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* arm/tms570: sci context has to be writable because it holds state variable.Pavel Pisa2015-02-042-4/+4
| | | | | | | | | | | | | | The structure tms570_sci_context holds state variable tx_chars_in_hw which holds if and how many characters (in the optional FIFO support for some Ti SCIs) are submitted into hardware. When field is not writable then code breaks when RTEMS is build for Flash area. The problem found and analyzed by Martin Galvan from tallertechnologies. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* stm32f4/.../stm32f105rc-testsuite.tcfg: Add more testsJoel Sherrill2015-01-231-0/+1
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* lpc24xx/.../lpc23xx_tli800-testsuite.tcfg: Add more testsJoel Sherrill2015-01-231-0/+7
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* lpc24xx/.../lpc2362-testsuite.tcfg: Add more testsJoel Sherrill2015-01-231-0/+2
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* lm3s69xx/.../lm3s6965-testsuite.tcfg: Add more testsJoel Sherrill2015-01-231-0/+1
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* lm3s69xx/.../lm3s3749-testsuite.tcfg: Add more testsJoel Sherrill2015-01-231-0/+2
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* bsp/altera-cyclone-v: Use proper free functionSebastian Huber2015-01-231-1/+1
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* bsp/beagle: Fix some warningsBen Gras2014-12-152-3/+3
| | | | | | | The extra includes in console_*.c are to solve a 'no previous prototype' warning. Solves #2212 in trac.
* bsp/lpc32xx: Fix memory mapSebastian Huber2014-12-151-1/+1
| | | | | | Fixes bug introduced with f0c564c5ae36da20b1543ae9db9e8fe9644a81c8. close #2218
* Update bug report URLSebastian Huber2014-12-0522-22/+22
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* beagle bsp: disable watchdog on am335xBen Gras2014-12-051-0/+9
| | | | | | | | | | | | On recent u-boots, the watchdog is turned on / left enabled. The Beaglebone Black rev. C ships with such a u-boot internally so any application booting from it must disable the watchdog. Therefore this change is needed to boot an RTEMS app out-of-the-box on a BBB Rev C - otherwise the user button must be held during boot (to bypass the stock uboot) or the internal uboot must be updated. To allow for a better out-of-the-box experience, we just turn off the watchdog.
* bsps/arm: Add .nocache sectionSebastian Huber2014-11-2756-184/+136
| | | | | This section can be use to provide a cache coherent memory area via rtems_cache_coherent_add_area().
* bsps/arm: L2C 310 avoid infinite loopsSebastian Huber2014-11-251-0/+8
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* bsps/arm: Enable L2C for Cortex-A9 MPCore BSPsSebastian Huber2014-11-2011-65/+98
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* bsps/arm: L2C 310 drop exclusive cache supportSebastian Huber2014-11-201-71/+50
| | | | Optimize locking.
* bsps/arm: L1 cache support changesSebastian Huber2014-11-201-16/+21
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* bsps/arm: L2C 310 compile-time errata 588369Sebastian Huber2014-11-201-49/+19
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* bsps/arm: L2C 310 compile-time errata 753970Sebastian Huber2014-11-201-71/+43
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* bsps/arm: L2C 310 exclusive config is fatalSebastian Huber2014-11-201-7/+16
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* bsps/arm: L2C 310 use l2c_310_* prefix throughoutSebastian Huber2014-11-201-99/+99
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* bsps/arm: L2C 310 use L2C_310_* prefix throughoutSebastian Huber2014-11-201-232/+232
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* bsps/arm: L2C 310 add compile time checksSebastian Huber2014-11-203-84/+75
| | | | Simplify initialization. Replace some assert() with fatal errors.
* bsps/arm: L2C 310 delete invalid linkSebastian Huber2014-11-201-2/+0
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* bsps/arm: L2C 310 simplify and remove white spaceSebastian Huber2014-11-201-292/+177
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* bsps/arm: L2C 310 rename BSP_ARM_L2CC_BASESebastian Huber2014-11-203-28/+28
| | | | Rename BSP_ARM_L2CC_BASE to BSP_ARM_L2C_310_BASE.
* bsp/xilinx-zynq: Add Cadence I2C bus driverSebastian Huber2014-11-206-0/+645
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* bsp/xilinx-zynq: Add zync_clock_cpu_1x()Sebastian Huber2014-11-203-2/+14
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* bsp/xilinx-zynq: Rename BSP_ARM_A9MPCORE_UARTCLKSebastian Huber2014-11-202-5/+5
| | | | | Rename BSP_ARM_A9MPCORE_UARTCLK to ZYNQ_CLOCK_UART since this clock has nothing to do with the Cortex-A9 MPCore.
* bsp/xilinx-zynq: Adjust BSP_ARM_A9MPCORE_PERIPHCLKSebastian Huber2014-11-201-1/+1
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* bsps/arm: Adjust stacks for ARMv4Sebastian Huber2014-11-202-19/+7
| | | | | | | | Reduce non-IRQ stacks to size zero. All non-IRQ stacks overlap now the IRQ stack. This is all right since the SVC stack is used only during startup and here interrupts are disabled. The other exception stacks lead to a system termination by default, so we can here also use the IRQ stack since interrupts are disabled on exception entry.
* ARM removed shared/abort from several ARM BSPsAlan Cudmore2014-11-206-54/+55
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* lpc23xx_tli800-testsuite.tcfg: Add dl02Joel Sherrill2014-11-051-0/+1
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* lpc2362-testsuite.tcfg: Add dl02Joel Sherrill2014-11-051-0/+1
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* lpc1768_mbed_ahb_ram_eth-testsuite.tcfg: Add a handful more testsJoel Sherrill2014-11-051-0/+8
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