Commit message (Collapse) | Author | Age | Files | Lines | |
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* | bsps/arm: Update due to API changes | Sebastian Huber | 2015-07-21 | 1 | -4/+4 |
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* | bsps/arm: Update due to API changes | Sebastian Huber | 2015-06-26 | 1 | -2/+2 |
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* | arm/shared/lpc/clock/lpc-clock-config.c: Remove unused variable warning | Joel Sherrill | 2015-05-21 | 1 | -1/+0 |
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* | bsps: Convert clock drivers to use a timecounter | Alexander Krutwig | 2015-05-20 | 3 | -75/+75 |
| | | | | Update #2271. | ||||
* | ARM: Add BSP_START_NEEDS_REGISTER_INITIALIZATION | Martin Galvan | 2015-02-27 | 2 | -0/+133 |
| | | | | | | | | | | | | | This patch adds the macro BSP_START_NEEDS_REGISTER_INITIALIZATION and three hooks for BSP-specific register init code to arm/shared/start.S. Said hooks are bsp_start_init_registers_core (intended for initializing the ARM core registers), bsp_start_init_registers_banked_fiq (for the FIQ mode banked registers) and bsp_start_init_registers_vfp (for the FPU registers). BSP_START_NEEDS_REGISTER_INITIALIZATION would be defined in a BSP's configure.ac (so that it appears in its bspopts.h). This patch also adds the register init code required by the TMS570. We've tested it with the tms570ls3137_hdk.cfg config and it works fine. | ||||
* | ARM: Support VFP-D16 | Martin Galvan | 2015-02-20 | 1 | -3/+5 |
| | | | | | | | | | This patch allows the existing FPU code to support both VFP-D16 and VFP-D32. According to ARM, writes to D32DIS are ignored for D16 so there's no need to enclose the bic instruction with an #ifdef. We tested it on a TMS570LS3137 using TI initialization code and it works fine. Signed-off by: Martin Galvan <martin.galvan@tallertechnologies.com> | ||||
* | score: Add _CPU_SMP_Prepare_start_multitasking() | Sebastian Huber | 2015-02-17 | 1 | -0/+5 |
| | | | | Update #2268. | ||||
* | bsps/arm: Add .nocache section | Sebastian Huber | 2014-11-27 | 3 | -1/+30 |
| | | | | | This section can be use to provide a cache coherent memory area via rtems_cache_coherent_add_area(). | ||||
* | bsps/arm: L2C 310 avoid infinite loops | Sebastian Huber | 2014-11-25 | 1 | -0/+8 |
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* | bsps/arm: Enable L2C for Cortex-A9 MPCore BSPs | Sebastian Huber | 2014-11-20 | 1 | -9/+9 |
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* | bsps/arm: L2C 310 drop exclusive cache support | Sebastian Huber | 2014-11-20 | 1 | -71/+50 |
| | | | | Optimize locking. | ||||
* | bsps/arm: L1 cache support changes | Sebastian Huber | 2014-11-20 | 1 | -16/+21 |
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* | bsps/arm: L2C 310 compile-time errata 588369 | Sebastian Huber | 2014-11-20 | 1 | -49/+19 |
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* | bsps/arm: L2C 310 compile-time errata 753970 | Sebastian Huber | 2014-11-20 | 1 | -71/+43 |
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* | bsps/arm: L2C 310 exclusive config is fatal | Sebastian Huber | 2014-11-20 | 1 | -7/+16 |
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* | bsps/arm: L2C 310 use l2c_310_* prefix throughout | Sebastian Huber | 2014-11-20 | 1 | -99/+99 |
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* | bsps/arm: L2C 310 use L2C_310_* prefix throughout | Sebastian Huber | 2014-11-20 | 1 | -232/+232 |
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* | bsps/arm: L2C 310 add compile time checks | Sebastian Huber | 2014-11-20 | 1 | -81/+68 |
| | | | | Simplify initialization. Replace some assert() with fatal errors. | ||||
* | bsps/arm: L2C 310 delete invalid link | Sebastian Huber | 2014-11-20 | 1 | -2/+0 |
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* | bsps/arm: L2C 310 simplify and remove white space | Sebastian Huber | 2014-11-20 | 1 | -292/+177 |
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* | bsps/arm: L2C 310 rename BSP_ARM_L2CC_BASE | Sebastian Huber | 2014-11-20 | 1 | -26/+26 |
| | | | | Rename BSP_ARM_L2CC_BASE to BSP_ARM_L2C_310_BASE. | ||||
* | bsps/arm: Adjust stacks for ARMv4 | Sebastian Huber | 2014-11-20 | 2 | -19/+7 |
| | | | | | | | | Reduce non-IRQ stacks to size zero. All non-IRQ stacks overlap now the IRQ stack. This is all right since the SVC stack is used only during startup and here interrupts are disabled. The other exception stacks lead to a system termination by default, so we can here also use the IRQ stack since interrupts are disabled on exception entry. | ||||
* | ARM removed shared/abort from several ARM BSPs | Alan Cudmore | 2014-11-20 | 3 | -50/+55 |
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* | bsps/arm: Convert PL011 and PL050 console drivers | Sebastian Huber | 2014-10-14 | 4 | -110/+98 |
| | | | | Use Termios device API. | ||||
* | bsps/arm: Move abort stack | Sebastian Huber | 2014-10-13 | 1 | -4/+4 |
| | | | | | Move abort stack above the other exception stacks to use them just in case. | ||||
* | arm/shared/abort/abort.c: Fix warnings and clean up | Joel Sherrill | 2014-10-09 | 1 | -17/+28 |
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* | bsps/arm: Add a9mpcore_clock_initialize_early() | Sebastian Huber | 2014-09-10 | 2 | -5/+10 |
| | | | | | This is necessary to use the CPU counter converter even in case no clock driver is present, e.g. in tmcontext01. | ||||
* | bsps/arm: Fix get cache size | Sebastian Huber | 2014-09-10 | 1 | -4/+6 |
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* | bsps/arm: Fix invalidate instruction cache | Sebastian Huber | 2014-09-10 | 1 | -33/+2 |
| | | | | | | | Do not invalidate the entire L2 cache since it is a uniform cache in _CPU_cache_invalidate_entire_instruction(). For consitency do not touch the L2 cache even for the range function _CPU_cache_invalidate_instruction_range(). | ||||
* | bsps/arm: Fix GIC tm27 support | Sebastian Huber | 2014-09-10 | 1 | -15/+29 |
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* | arm: Add support for FPv4-SP floating point unit | Sebastian Huber | 2014-08-12 | 1 | -0/+15 |
| | | | | | This floating point unit is available in Cortex-M4 processors and defined by ARMv7-M. This adds basic support for other VFP-D16 variants. | ||||
* | Common ARM A8 code. | Chris Johns | 2014-07-16 | 1 | -0/+55 |
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* | bsps/arm: Rename bsp_mm_config_table | Sebastian Huber | 2014-07-01 | 2 | -4/+6 |
| | | | | | | Rename bsp_mm_config_table to arm_cp15_start_mmu_config_table and rename bsp_mm_config_table_size to arm_cp15_start_mmu_config_table_size to be in line with the other names in <bsp/arm-cp15-start.h>. | ||||
* | bsps/arm: Fix Cortex-A9 MPCore clock driver | Sebastian Huber | 2014-06-06 | 1 | -9/+18 |
| | | | | | | The nanoseconds extension returned wrong values on secondary processors since some of the global timer registeres are banked. Use global variables instead. | ||||
* | bsps/arm: Change L2 cache initialization | Sebastian Huber | 2014-06-06 | 2 | -50/+1 |
| | | | | | Do not touch the L1 caches since they have been initialized by the start hooks. | ||||
* | bsps/arm: Define ARM_CP15_TEXT_SECTION | Sebastian Huber | 2014-06-06 | 3 | -43/+5 |
| | | | | | Define ARM_CP15_TEXT_SECTION to BSP_START_TEXT_SECTION so that the start code is in the right section. | ||||
* | bsps/arm: Simplify L1 caches support | Sebastian Huber | 2014-06-05 | 1 | -55/+12 |
| | | | | Delete superfluous/incorrect interrupt disable/enable. | ||||
* | bsps/arm: Cortex-A9 MPCore start | Sebastian Huber | 2014-06-05 | 1 | -0/+5 |
| | | | | Invalidate entire branch predictor array. | ||||
* | bsps/arm: Cortex-A9 MPCore start | Sebastian Huber | 2014-06-05 | 1 | -4/+4 |
| | | | | Enable SCU only on the boot processor. | ||||
* | bsps/arm: Cortex-A9 MPCore start | Sebastian Huber | 2014-06-05 | 1 | -6/+13 |
| | | | | Add arm_a9mpcore_start_enable_smp_in_auxiliary_control(). | ||||
* | bsps/arm: Simplify Cortex-A9 MPCore start | Sebastian Huber | 2014-06-05 | 1 | -31/+32 |
| | | | | | Add arm_a9mpcore_start_on_secondary_processor(). Rely on error checks in _SMP_Start_multitasking_on_secondary_processor(). | ||||
* | bsp/arm: Broadcast cache maintenances | Ralf Kirchner | 2014-05-28 | 1 | -1/+1 |
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* | bsps/arm: Declare return types | Sebastian Huber | 2014-05-07 | 1 | -7/+8 |
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* | bsps: Fix TLS support in linker command files | Sebastian Huber | 2014-04-22 | 1 | -1/+3 |
| | | | | | The TLS section symbols had wrong values in case of an empty TLS data section and a nonempty TLS BSS section. | ||||
* | bsp/arm: Cleanup L2 cache handling | Ralf Kirchner | 2014-04-17 | 1 | -38/+7 |
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* | bsp/arm: Correct L2 cache enable method | Ralf Kirchner | 2014-04-17 | 1 | -53/+48 |
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* | bsp/arm: Add cache size methods | Ralf Kirchner | 2014-04-17 | 2 | -0/+115 |
| | | | | Add new methods which deliver the cache sizes of for supported cache levels. | ||||
* | bsp/arm: Add L2 cache locking | Ralf Kirchner | 2014-04-17 | 1 | -9/+34 |
| | | | | This level 2 cache is a shared data and instruction cache and thus needs locking. | ||||
* | bsp/arm: Remove unused cache store methods | Ralf Kirchner | 2014-04-17 | 2 | -30/+0 |
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* | bsp/arm: Correct cache misalignment handling | Ralf Kirchner | 2014-04-17 | 2 | -32/+60 |
| | | | | Correct misalignment handling and prepare for locking. |