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2016-10-02bsps/arm: Export bsp_start_hook_0_done symbol from ARM start.S.Pavel Pisa1-0/+1
The symbol can be used by bsp_start_hook_0 when complete RAM memory is initialization and overwritten during BSP self-test. The test overwrites even memory used to store return address / link register and regular resturn from bsp_start_hook_0 is not possible then.
2016-10-02bsps/arm: Support recent bootloaders starting kernel in HYP modePavel Pisa5-7/+175
When HYP mode is detected at startup then setup HYP mode vectors table (for future extensions) clean exceptions switching to HYP mode and switch CPU to ARM SVC mode. BSPs which want to use this support need to include next option in their configure.ac RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1]) RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode]) AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1") and need to include next lines in corresponding Makefile.am if BSP_START_IN_HYP_SUPPORT libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S endif Updates #2783
2016-10-02libbsp/arm: Add the TTB table to the default MMU set up as read/write.Chris Johns1-0/+4
This lets the table be changed at runtime for dynamic loading and debugger support. Closes #2775.
2016-10-02bsps/arm: Fix basic cache support for SMPSebastian Huber1-8/+8
Updates #2782 Updates #2783
2016-10-02bsps/arm: remove lock in arm_cp15_set_translation_table_entries().Pavel Pisa1-9/+1
Protection by rtems_interrupt_disable() is incompatible with SMP build. Actual page table entries manipulation function does not need locking and disabling cache and can be run concurrently even on multiple CPUs as long as changes do not modify same region. If the function is called from more threads/CPUs to modify same region with different mapping options concurrently then there is problem at another level of virtual address space management and has to be solved by mutex or other locking at that level. Updates #2782 Updates #2783
2016-10-02arm/bsps: CP15 and basic cache support entire cache clean for more ↵Pavel Pisa2-4/+24
architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4). Updates #2782 Updates #2783
2016-10-02bsps/arm: do not disable MMU during translation table management operations.Pavel Pisa1-8/+42
Disabling MMU requires complex cache flushing and invalidation operations. There is almost no way how to do that right on SMP system without stopping all other CPUs. On the other hand, there is documented sequence of operations which should be used according to ARM manual and it guarantees even distribution of maintenance operations to other cores for last generation of Cortex-A cores with multiprocessor extension. This change could require addition of appropriate entry to arm_cp15_start_mmu_config_table for some BSPs to ensure that MMU table stays accessible after MMU is enabled { .begin = (uint32_t) bsp_translation_table_base, .end = (uint32_t) bsp_translation_table_base + 0x4000, .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED } Updates #2782 Updates #2783
2016-10-02bsps/arm: basic on core cache support changed to use l1 functions.Pavel Pisa2-45/+69
The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem. Updates #2783 Updates #2782
2016-10-02bsps/arm: Change code to explicit selection of cache implementation for ARM ↵Pavel Pisa1-0/+134
BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support Updates #2782 Updates #2783
2016-10-02bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.Pavel Pisa1-0/+4
Updates #2782 Updates #2783
2016-01-27score: Fix simple timecounter supportSebastian Huber1-14/+37
Close #2502.
2016-01-18bsps/arm: Fix broken switch statementSebastian Huber1-4/+5
Close #2530.
2015-07-21bsps/arm: Update due to API changesSebastian Huber1-4/+4
2015-06-26bsps/arm: Update due to API changesSebastian Huber1-2/+2
2015-05-21arm/shared/lpc/clock/lpc-clock-config.c: Remove unused variable warningJoel Sherrill1-1/+0
2015-05-20bsps: Convert clock drivers to use a timecounterAlexander Krutwig3-75/+75
Update #2271.
2015-02-27ARM: Add BSP_START_NEEDS_REGISTER_INITIALIZATIONMartin Galvan2-0/+133
This patch adds the macro BSP_START_NEEDS_REGISTER_INITIALIZATION and three hooks for BSP-specific register init code to arm/shared/start.S. Said hooks are bsp_start_init_registers_core (intended for initializing the ARM core registers), bsp_start_init_registers_banked_fiq (for the FIQ mode banked registers) and bsp_start_init_registers_vfp (for the FPU registers). BSP_START_NEEDS_REGISTER_INITIALIZATION would be defined in a BSP's configure.ac (so that it appears in its bspopts.h). This patch also adds the register init code required by the TMS570. We've tested it with the tms570ls3137_hdk.cfg config and it works fine.
2015-02-20ARM: Support VFP-D16Martin Galvan1-3/+5
This patch allows the existing FPU code to support both VFP-D16 and VFP-D32. According to ARM, writes to D32DIS are ignored for D16 so there's no need to enclose the bic instruction with an #ifdef. We tested it on a TMS570LS3137 using TI initialization code and it works fine. Signed-off by: Martin Galvan <martin.galvan@tallertechnologies.com>
2015-02-17score: Add _CPU_SMP_Prepare_start_multitasking()Sebastian Huber1-0/+5
Update #2268.
2014-11-27bsps/arm: Add .nocache sectionSebastian Huber3-1/+30
This section can be use to provide a cache coherent memory area via rtems_cache_coherent_add_area().
2014-11-25bsps/arm: L2C 310 avoid infinite loopsSebastian Huber1-0/+8
2014-11-20bsps/arm: Enable L2C for Cortex-A9 MPCore BSPsSebastian Huber1-9/+9
2014-11-20bsps/arm: L2C 310 drop exclusive cache supportSebastian Huber1-71/+50
Optimize locking.
2014-11-20bsps/arm: L1 cache support changesSebastian Huber1-16/+21
2014-11-20bsps/arm: L2C 310 compile-time errata 588369Sebastian Huber1-49/+19
2014-11-20bsps/arm: L2C 310 compile-time errata 753970Sebastian Huber1-71/+43
2014-11-20bsps/arm: L2C 310 exclusive config is fatalSebastian Huber1-7/+16
2014-11-20bsps/arm: L2C 310 use l2c_310_* prefix throughoutSebastian Huber1-99/+99
2014-11-20bsps/arm: L2C 310 use L2C_310_* prefix throughoutSebastian Huber1-232/+232
2014-11-20bsps/arm: L2C 310 add compile time checksSebastian Huber1-81/+68
Simplify initialization. Replace some assert() with fatal errors.
2014-11-20bsps/arm: L2C 310 delete invalid linkSebastian Huber1-2/+0
2014-11-20bsps/arm: L2C 310 simplify and remove white spaceSebastian Huber1-292/+177
2014-11-20bsps/arm: L2C 310 rename BSP_ARM_L2CC_BASESebastian Huber1-26/+26
Rename BSP_ARM_L2CC_BASE to BSP_ARM_L2C_310_BASE.
2014-11-20bsps/arm: Adjust stacks for ARMv4Sebastian Huber2-19/+7
Reduce non-IRQ stacks to size zero. All non-IRQ stacks overlap now the IRQ stack. This is all right since the SVC stack is used only during startup and here interrupts are disabled. The other exception stacks lead to a system termination by default, so we can here also use the IRQ stack since interrupts are disabled on exception entry.
2014-11-20ARM removed shared/abort from several ARM BSPsAlan Cudmore3-50/+55
2014-10-14bsps/arm: Convert PL011 and PL050 console driversSebastian Huber4-110/+98
Use Termios device API.
2014-10-13bsps/arm: Move abort stackSebastian Huber1-4/+4
Move abort stack above the other exception stacks to use them just in case.
2014-10-09arm/shared/abort/abort.c: Fix warnings and clean upJoel Sherrill1-17/+28
2014-09-10bsps/arm: Add a9mpcore_clock_initialize_early()Sebastian Huber2-5/+10
This is necessary to use the CPU counter converter even in case no clock driver is present, e.g. in tmcontext01.
2014-09-10bsps/arm: Fix get cache sizeSebastian Huber1-4/+6
2014-09-10bsps/arm: Fix invalidate instruction cacheSebastian Huber1-33/+2
Do not invalidate the entire L2 cache since it is a uniform cache in _CPU_cache_invalidate_entire_instruction(). For consitency do not touch the L2 cache even for the range function _CPU_cache_invalidate_instruction_range().
2014-09-10bsps/arm: Fix GIC tm27 supportSebastian Huber1-15/+29
2014-08-12arm: Add support for FPv4-SP floating point unitSebastian Huber1-0/+15
This floating point unit is available in Cortex-M4 processors and defined by ARMv7-M. This adds basic support for other VFP-D16 variants.
2014-07-16Common ARM A8 code.Chris Johns1-0/+55
2014-07-01bsps/arm: Rename bsp_mm_config_tableSebastian Huber2-4/+6
Rename bsp_mm_config_table to arm_cp15_start_mmu_config_table and rename bsp_mm_config_table_size to arm_cp15_start_mmu_config_table_size to be in line with the other names in <bsp/arm-cp15-start.h>.
2014-06-06bsps/arm: Fix Cortex-A9 MPCore clock driverSebastian Huber1-9/+18
The nanoseconds extension returned wrong values on secondary processors since some of the global timer registeres are banked. Use global variables instead.
2014-06-06bsps/arm: Change L2 cache initializationSebastian Huber2-50/+1
Do not touch the L1 caches since they have been initialized by the start hooks.
2014-06-06bsps/arm: Define ARM_CP15_TEXT_SECTIONSebastian Huber3-43/+5
Define ARM_CP15_TEXT_SECTION to BSP_START_TEXT_SECTION so that the start code is in the right section.
2014-06-05bsps/arm: Simplify L1 caches supportSebastian Huber1-55/+12
Delete superfluous/incorrect interrupt disable/enable.
2014-06-05bsps/arm: Cortex-A9 MPCore startSebastian Huber1-0/+5
Invalidate entire branch predictor array.
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