| Commit message (Collapse) | Author | Age | Files | Lines |
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The basic data and instruction rage functions should be compatible
for all ARMv4,5,6,7 functions. On the other hand, some functions
are not portable, for example arm_cp15_data_cache_test_and_clean()
and arm_cp15_data_cache_invalidate() for all versions and there
has to be specialized version for newer cores.
arm_cache_l1_properties_for_level uses CCSIDR which is not present
on older chips.
Actual version is only experimental, needs more changes
and problem has been found on RPi1 with dlopen so there seems
to be real problem.
Updates #2783
Updates #2782
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BSPs.
The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.
The ARM targets equipped by cache should include
appropriate implementation.
Next options are available for now
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
basic ARM cache integrated on the CPU core directly
which requires only CP15 oparations
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
support for case where ARM L2C-310 cache controller
is used. It is accessible as mmaped peripheral.
c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
Cortex-M specific cache support
Updates #2782
Updates #2783
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Updates #2782
Updates #2783
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Close #2502.
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Close #2530.
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Update #2271.
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This patch adds the macro BSP_START_NEEDS_REGISTER_INITIALIZATION and
three hooks for BSP-specific register init code to arm/shared/start.S.
Said hooks are bsp_start_init_registers_core (intended for initializing
the ARM core registers), bsp_start_init_registers_banked_fiq (for the
FIQ mode banked registers) and bsp_start_init_registers_vfp (for the FPU
registers). BSP_START_NEEDS_REGISTER_INITIALIZATION would be defined in
a BSP's configure.ac (so that it appears in its bspopts.h).
This patch also adds the register init code required by the TMS570.
We've tested it with the tms570ls3137_hdk.cfg config and it works fine.
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This patch allows the existing FPU code to support both VFP-D16 and
VFP-D32. According to ARM, writes to D32DIS are ignored for D16 so
there's no need to enclose the bic instruction with an #ifdef. We tested
it on a TMS570LS3137 using TI initialization code and it works fine.
Signed-off by: Martin Galvan <martin.galvan@tallertechnologies.com>
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Update #2268.
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This section can be use to provide a cache coherent memory area via
rtems_cache_coherent_add_area().
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Optimize locking.
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Simplify initialization. Replace some assert() with fatal errors.
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Rename BSP_ARM_L2CC_BASE to BSP_ARM_L2C_310_BASE.
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Reduce non-IRQ stacks to size zero. All non-IRQ stacks overlap now the
IRQ stack. This is all right since the SVC stack is used only during
startup and here interrupts are disabled. The other exception stacks
lead to a system termination by default, so we can here also use the IRQ
stack since interrupts are disabled on exception entry.
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Use Termios device API.
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Move abort stack above the other exception stacks to use them just in
case.
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This is necessary to use the CPU counter converter even in case no clock
driver is present, e.g. in tmcontext01.
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Do not invalidate the entire L2 cache since it is a uniform cache in
_CPU_cache_invalidate_entire_instruction(). For consitency do not touch
the L2 cache even for the range function
_CPU_cache_invalidate_instruction_range().
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This floating point unit is available in Cortex-M4 processors and
defined by ARMv7-M. This adds basic support for other VFP-D16 variants.
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Rename bsp_mm_config_table to arm_cp15_start_mmu_config_table and
rename bsp_mm_config_table_size to arm_cp15_start_mmu_config_table_size
to be in line with the other names in <bsp/arm-cp15-start.h>.
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The nanoseconds extension returned wrong values on secondary processors
since some of the global timer registeres are banked. Use global
variables instead.
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Do not touch the L1 caches since they have been initialized by the start
hooks.
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Define ARM_CP15_TEXT_SECTION to BSP_START_TEXT_SECTION so that the
start code is in the right section.
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Delete superfluous/incorrect interrupt disable/enable.
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Invalidate entire branch predictor array.
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Enable SCU only on the boot processor.
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Add arm_a9mpcore_start_enable_smp_in_auxiliary_control().
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Add arm_a9mpcore_start_on_secondary_processor(). Rely on error checks
in _SMP_Start_multitasking_on_secondary_processor().
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The TLS section symbols had wrong values in case of an empty TLS data
section and a nonempty TLS BSS section.
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