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* bsps/arm: Support recent bootloaders starting kernel in HYP modePavel Pisa2016-10-022-2/+15
| | | | | | | | | | | | | | | | | | | | | When HYP mode is detected at startup then setup HYP mode vectors table (for future extensions) clean exceptions switching to HYP mode and switch CPU to ARM SVC mode. BSPs which want to use this support need to include next option in their configure.ac RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1]) RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode]) AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1") and need to include next lines in corresponding Makefile.am if BSP_START_IN_HYP_SUPPORT libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S endif Updates #2783
* libbsp/arm: Add the TTB table to the default MMU set up as read/write.Chris Johns2016-10-021-0/+4
| | | | | | | This lets the table be changed at runtime for dynamic loading and debugger support. Closes #2775.
* arm/bsps: CP15 and basic cache support entire cache clean for more ↵Pavel Pisa2016-10-021-1/+5
| | | | | | | | | | | | | | | | | | | | architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4). Updates #2782 Updates #2783
* bsps/arm: basic on core cache support changed to use l1 functions.Pavel Pisa2016-10-021-42/+29
| | | | | | | | | | | | | | | | | The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem. Updates #2783 Updates #2782
* bsps/arm: Fix broken switch statementSebastian Huber2016-01-181-4/+5
| | | | Close #2530.
* bsps/arm: Update due to API changesSebastian Huber2015-07-211-4/+4
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* bsps/arm: Add .nocache sectionSebastian Huber2014-11-272-1/+17
| | | | | This section can be use to provide a cache coherent memory area via rtems_cache_coherent_add_area().
* bsps/arm: L1 cache support changesSebastian Huber2014-11-201-16/+21
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* bsps/arm: Convert PL011 and PL050 console driversSebastian Huber2014-10-142-6/+28
| | | | Use Termios device API.
* bsps/arm: Add a9mpcore_clock_initialize_early()Sebastian Huber2014-09-101-1/+10
| | | | | This is necessary to use the CPU counter converter even in case no clock driver is present, e.g. in tmcontext01.
* bsps/arm: Fix GIC tm27 supportSebastian Huber2014-09-101-15/+29
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* Common ARM A8 code.Chris Johns2014-07-161-0/+55
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* bsps/arm: Rename bsp_mm_config_tableSebastian Huber2014-07-011-2/+4
| | | | | | Rename bsp_mm_config_table to arm_cp15_start_mmu_config_table and rename bsp_mm_config_table_size to arm_cp15_start_mmu_config_table_size to be in line with the other names in <bsp/arm-cp15-start.h>.
* bsps/arm: Change L2 cache initializationSebastian Huber2014-06-061-47/+0
| | | | | Do not touch the L1 caches since they have been initialized by the start hooks.
* bsps/arm: Define ARM_CP15_TEXT_SECTIONSebastian Huber2014-06-062-42/+1
| | | | | Define ARM_CP15_TEXT_SECTION to BSP_START_TEXT_SECTION so that the start code is in the right section.
* bsps/arm: Simplify L1 caches supportSebastian Huber2014-06-051-55/+12
| | | | Delete superfluous/incorrect interrupt disable/enable.
* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-0/+5
| | | | Invalidate entire branch predictor array.
* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-4/+4
| | | | Enable SCU only on the boot processor.
* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-6/+13
| | | | Add arm_a9mpcore_start_enable_smp_in_auxiliary_control().
* bsps/arm: Simplify Cortex-A9 MPCore startSebastian Huber2014-06-051-31/+32
| | | | | Add arm_a9mpcore_start_on_secondary_processor(). Rely on error checks in _SMP_Start_multitasking_on_secondary_processor().
* bsp/arm: Broadcast cache maintenancesRalf Kirchner2014-05-281-1/+1
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* bsps/arm: Declare return typesSebastian Huber2014-05-071-7/+8
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* bsp/arm: Add cache size methodsRalf Kirchner2014-04-171-0/+33
| | | | Add new methods which deliver the cache sizes of for supported cache levels.
* bsp/arm: Remove unused cache store methodsRalf Kirchner2014-04-171-9/+0
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* bsp/arm: Correct cache misalignment handlingRalf Kirchner2014-04-171-6/+6
| | | | Correct misalignment handling and prepare for locking.
* bsp/arm: Consistenly same handling for flushingRalf Kirchner2014-04-171-2/+2
| | | | | It is importeant to consistently apply the same handling for flushing within level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
* bsp/arm: RTEMS_SMP to arm erratum 764369 detectionRalf Kirchner2014-04-173-10/+8
| | | | Move the RTEMS_SMP conditional compilation to the detection method of arm erratum 764369
* bsp/arm: Erratum 764369 after enabling SCURalf Kirchner2014-04-171-1/+1
| | | | Execute the SCU part of the workaround of arm erratum 764368 after the SCU was enabled.
* bsp/arm: Correct detection of arm erratum 764368Ralf Kirchner2014-04-171-0/+1
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* bsp/arm: Cleanup L1 cacheRalf Kirchner2014-04-171-2/+2
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* Change all references of rtems.com to rtems.org.Chris Johns2014-03-2117-17/+17
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* bsp/arm: Add handling for level 2 L2C-310 cache controllerRalf Kirchner2014-03-131-0/+483
| | | | | | arm-l2c-310/cache_.h contains the handling for the L2C-310 level 2 cache controller from arm. It references the arm level 1 cache handling in the new file arm-cache-l1.h.
* bsp/arm: Add SCU errata handling for L2C-310 cacheRalf Kirchner2014-03-132-10/+36
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* bsp/arm: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+279
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* bsp/arm: Add linker symbol bsp_processor_countRalf Kirchner2014-03-131-0/+2
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* bsp/arm: Separate setup for translation tableRalf Kirchner2014-03-131-4/+20
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* bsp/arm: Invalidate SCURalf Kirchner2014-03-132-1/+25
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* score: Rename rtems_smp_process_interrupt()Sebastian Huber2014-02-191-1/+0
| | | | | | Rename rtems_smp_process_interrupt() into _SMP_Inter_processor_interrupt_handler(). Delete unused header file <rtems/bspsmp.h>.
* score: Rename rtems_smp_secondary_cpu_initialize()Sebastian Huber2014-02-191-1/+2
| | | | | | Rename rtems_smp_secondary_cpu_initialize() into _SMP_Start_multitasking_on_secondary_processor(). Move declaration to <rtems/score/smpimpl.h>.
* bsps/arm: Use Global Timer for Cortex-A9 MPCoreSebastian Huber2014-02-102-4/+23
| | | | | | Use the Global Timer for the Cortex-A9 MPCore clock driver instead of the Private Timer. This enables a consistent nanoseconds since last context switch value across all processors.
* bsps/arm: Use ALIGN_WITH_INPUTSebastian Huber2014-01-132-13/+0
| | | | | | | | | | | | | The ALIGN_WITH_INPUT helps to make this linker script more reliable. See also: https://sourceware.org/ml/binutils/2013-06/msg00246.html https://sourceware.org/binutils/docs-2.24/ld/Forced-Output-Alignment.html#Forced-Output-Alignment This reverts commit 4a9e52eefc510d7022ddc61c4ecde8db6b9a0217. This reverts commit 1ab4f76900d012b5a9dbce2851add060f11ce13a.
* bsps/arm: Use handlers for PL111 set up/tear downSebastian Huber2014-01-101-5/+5
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* libbsp misc: Fix comment formattingJoel Sherrill2013-12-301-6/+6
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* libbsp/arm: add doxygen to arm shared headersSzkocsovszki Zsolt2013-12-2213-0/+112
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* arm/a9mpcore: Add support to get the clock via a weak linkage function.Chris Johns2013-12-191-0/+29
| | | | | | This allows an application to provide a localised clock freq with needing to go down the BSP opts path. This is important with the Zynq where the Xilinx tools generate the frequency.
* Revert "bsps/arm: Use ALIGN_WITH_INPUT"Chris Johns2013-12-192-0/+13
| | | | | | | This reverts commit 287bbb65afd24ffc6254ae5f328733213f184205. Conflicts: c/src/lib/libbsp/arm/shared/startup/linkcmds.base
* bsps/arm: Use ALIGN_WITH_INPUTSebastian Huber2013-12-162-13/+0
| | | | This requires at least Binutils 2.24.
* arm shared: Add bsp_translation_table_end the linker symbols.Chris Johns2013-12-101-0/+1
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* doxygen: refactored doxygen in libbsp to illustrate new rule setDaniel Ramirez2013-12-092-12/+4
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* doxygen: refactored doxygen in libbsp/arm/lpc32xxDaniel Ramirez2013-11-291-0/+9
| | | | | | | | This patch refactors a lot of the existing doxygen within libbsp/arm/lpc32xx. Much of this refactoring was just renaming of existing groups to conform to a more consistent naming structure. With the addition of a doxygen header for tm27.h, all files within lpc32xx belong to doxygen group now. lpc32xx should be used a reference for adding doxygen to other bsps.
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