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* arm/raspberrypi: minimized mainline patch move MMU in front of application ↵Pavel Pisa2016-10-022-3/+4
| | | | | | | | | | | | | | | | image and correct RPi2 boot on 4.11 branch. This is minimized version of mainline patch arm/raspberrypi: move MMU in front of application image to respect variable memory size. plus correction which has been part of other mainline patches. This is end of series which allows 4.11 to boot on Raspberry Pi. Closes #2782 Closes #2783
* arm/raspberrypi: change interrupt dispatch and enable to generic vector id ↵Pavel Pisa2016-10-022-43/+94
| | | | | | | | | | based approach. Using conditional branches to find bits is extremely inefficient and for asynchronous delivery of different interrupt sources lead to total confusion of branch prediction unit. Updates #2783
* arm/raspberrypi: remove duplicate setup of IRQ handler in the main ARM ↵Pavel Pisa2016-10-022-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | exception table. Exception table setup is processed by common CPU architecture support. For ARM architecture, it can be found in the file rtems/c/src/lib/libbsp/arm/shared/start/start.S and ends by bsp_vector_table_copy_done label. The actual tabel content can be found at bsp_start_vector_table_begin For ARMv7-A and even other variant with hypervisor mode support, it is even not necessary to copy table to address 0 at all because CP15 register can be used to specify alternative table start address arm_cp15_set_vector_base_address(&)bsp_start_vector_table_begin; ARMv7-M have register to set exception table base as well. Updates #2783
* arm/raspberrypi: ensure that correct RPI_PERIPHERAL_BASE is provided by ↵Pavel Pisa2016-10-022-0/+2
| | | | | | | | | | | | | raspberrypi.h If the raspberrypi.h has been included without preceding inclussion of bsp.h then BSP_IS_RPI2 has not been set for Raspberry Pi 2 BSP variant and bad things happen later. The patch includes bspopts.h by raspberrypi.h and even includes bsp.h in critical peripherals support. Updates #2783
* arm/raspberrypi: reorder and update MMU config table to nor force RW section ↵Pavel Pisa2016-10-021-9/+22
| | | | | | | | | | | later to RO. Enable even the first megabyte of SDRAM to be cache-able after problems with stale cache content has been resolved by previous commit. Because major part of application usually fits to the first megabyte this speedups test dhrystone application by factor 40. Updates #2783
* arm/raspberrypi: Enable HYP to SVC switch for this BSP.Pavel Pisa2016-10-022-0/+7
| | | | | | | This support is required when newer firmware is used on Raspberry Pi 2 boards. Updates #2783
* arm/raspberrypi: use cache manager operations to flush/invalidate all cache ↵Pavel Pisa2016-10-021-7/+7
| | | | | | | | | | | | levels. This fix strange behavior where some stale content has been stored in level 2 cache before RTEMS has been start from U-boot which has reappeared after MMU enable and shadow vector table at start of SDRAM. Updates #2782 Updates #2783
* bsps/arm: Change code to explicit selection of cache implementation for ARM ↵Pavel Pisa2016-10-022-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support Updates #2782 Updates #2783
* arm/raspberrypi: ensure that RTEMS application image can be started by U-boot.Pavel Pisa2016-10-022-1/+39
| | | | | | | | | | | | | | | | | | The current versions of U-boot start kernel/RTEMS application image with instruction and data caches enabled and it sets exception base register to new address after its self-relocation. ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ Included changes in bsp_start_hook_0 restore default state to allow RTEMS image to run after startup from newer U-boot version on Raspberry Pi. Clear interrupt enable registers in interrupt controller to ensure that RTEMS starts from well defined state. Updates #2783
* RaspberryPi: Use rtems_configuration_get_microseconds_per_tick to set clock ↵Jan Sommer2015-07-071-2/+4
| | | | | | | | counter timer interrupt was hard coded to 10 ms per tick. Fix uses the setting of CONFIGURE_MICROSECONDS_PER_TICK to compute the correct start value for the counter See for more information: http://permalink.gmane.org/gmane.os.rtems.user/22691
* Multiple bsp_specs: Change *(old_endfile) to %(old_endfile)Joel Sherrill2015-05-211-1/+1
| | | | | | Fix typo. closes 2345.
* bsps: Convert clock drivers to use a timecounterAlexander Krutwig2015-05-201-11/+1
| | | | Update #2271.
* Add hardware FPU flags for Raspberry Pi 2 BSPAlan Cudmore2015-04-091-1/+1
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* preliminary Raspberry Pi Model 2 supportAlan Cudmore2015-03-166-22/+55
| | | | | | | | | | | | | | | | | This patch adds a BSP variant for the Raspberry Pi 2. You can build both variants by configuring with the option --enable-rtemsbsp="raspberrypi2 raspberrypi" For the current BSP, the only change was the peripheral register base address and the compiler options. The raspberrypi/make/custom rules were re-factored: raspberrypi.inc -- Common rules raspberrypi.cfg -- Raspberry Pi 1 specific rule/optons raspberrypi2.cfg -- Raspberry Pi 2 specific rule/options I tested hello, ticker, unlimited, and paranoia on both the Pi (Model A+) and Pi 2.
* raspberrypi: Do not include default IRQ handler and BSP specific oneJoel Sherrill2015-03-061-1/+0
| | | | | | This was tripping a linker error in the dl0[12] tests. closes 2247.
* Update bug report URLSebastian Huber2014-12-051-1/+1
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* bsps/arm: Add .nocache sectionSebastian Huber2014-11-271-0/+2
| | | | | This section can be use to provide a cache coherent memory area via rtems_cache_coherent_add_area().
* ARM removed shared/abort from several ARM BSPsAlan Cudmore2014-11-201-1/+0
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* arm/raspberrypi: Fix warningsJoel Sherrill2014-10-202-64/+64
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* bsps: Fix build errorSebastian Huber2014-09-182-5/+0
| | | | Fix build error introduced in f535fe5311978af53635c2da8e5cb10ef9d78802.
* Use correct prototype of benchmark_timer_read()Joel Sherrill2014-09-161-2/+2
| | | | | | | | | | | | | | This change starts with removing the effectively empty file timerdrv.h. The prototypes for benchmark_timer_XXX() were in btimer.h which was not universally used. Thus every use of timerdrv.h had to be changed to btimer.h. Then the prototypes for benchmark_timer_read() had to be adjusted to return benchmark_timer_t rather than int or uint32_t. I took this opportunity to also correct the file headers to separate the copyright from the file description comments which is needed to ensure the copyright isn't propagated into Doxygen output.
* raspberrypi: Use shared bspreset.cJoel Sherrill2014-09-042-36/+1
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* Regenerate all preinstall.am files.Joel Sherrill2014-08-281-6/+6
| | | | | Apparently, at some point automake output changed and these were not updated.
* bsps/arm: Rename bsp_mm_config_tableSebastian Huber2014-07-011-7/+3
| | | | | | Rename bsp_mm_config_table to arm_cp15_start_mmu_config_table and rename bsp_mm_config_table_size to arm_cp15_start_mmu_config_table_size to be in line with the other names in <bsp/arm-cp15-start.h>.
* bsps/arm: Define ARM_CP15_TEXT_SECTIONSebastian Huber2014-06-061-0/+2
| | | | | Define ARM_CP15_TEXT_SECTION to BSP_START_TEXT_SECTION so that the start code is in the right section.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-2114-14/+14
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* bsp/raspberrypi: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+10
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* score: Add CPU counter supportSebastian Huber2014-02-141-0/+2
| | | | | | | | | Add a CPU counter interface to allow access to a free-running counter. It is useful to measure short time intervals. This can be used for example to enable profiling of critical low-level functions. Add two busy wait functions rtems_counter_delay_ticks() and rtems_counter_delay_nanoseconds() implemented via the CPU counter.
* doxygen: refactored doxygen in libbsp to illustrate new rule setDaniel Ramirez2013-12-091-1/+1
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* raspberrypi doxygen refactoringDaniel Ramirez2013-11-2714-18/+92
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* bsps/arm: ARMV7_MMU_DATA_READ_WRITE_SHAREABLESebastian Huber2013-10-271-12/+6
| | | | | Delete ARMV7_MMU_DATA_READ_WRITE_SHAREABLE and move RTEMS_SMP specific MMU attribute settings to arm-cp15.h.
* Modify raspberrypi mm_config_table to map GPIO and registers.Hesham AL-Matary2013-10-271-2/+6
| | | | | | | Changes include reverting back to setting all page-table section entries as invalid and modify mm_config_table to apply the correct memory attributes for raspbberypi memory sections at startup. The newly added entry at mm_config_table maps raspberrypi GPIO and other registers found at raspberrypi.h
* Shared MMU initialization for ARM BSPs and RaspberryPi MMU supportHesham AL-Matary2013-10-035-21/+92
| | | | | | | Add support for MMU initialization for RaspberryPi. Introduce new shared MMU configuration table that can be used by other BSPs that call the arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache function. Demonstrate the use of the generic table with RaspberryPi.
* raspberrypi.cfg: Remove CVS IdJoel Sherrill2013-09-161-2/+0
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* Use $(EXEEXT) [defaults to "exe"] to generate binariesNick Withers2013-08-091-2/+2
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* bsp/raspberrypi: Use shared start codeSebastian Huber2013-05-061-60/+2
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* bsp/raspberrypi: Enable unaligned accessAlan Cudmore2013-05-061-1/+1
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* bsp/raspberrypi: New BSPAlan Cudmore2013-03-2420-0/+1530
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