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BSPs.
The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.
The ARM targets equipped by cache should include
appropriate implementation.
Next options are available for now
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
basic ARM cache integrated on the CPU core directly
which requires only CP15 oparations
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
support for case where ARM L2C-310 cache controller
is used. It is accessible as mmaped peripheral.
c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
Cortex-M specific cache support
Updates #2782
Updates #2783
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flush_data_cache uses R0 directly but doesn't list it as a clobbered
register. Compiling with -O3 made this code break, since the function
that calls flush_data_cache already uses r0.
closes #2416.
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Fix typo.
closes 2345.
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Update #2271.
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unused and poorly named (no prefix) and colliding with sp68.
Closes #2302.
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The extra includes in console_*.c are to solve a 'no previous prototype'
warning.
Solves #2212 in trac.
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On recent u-boots, the watchdog is turned on / left enabled. The
Beaglebone Black rev. C ships with such a u-boot internally so any
application booting from it must disable the watchdog.
Therefore this change is needed to boot an RTEMS app out-of-the-box
on a BBB Rev C - otherwise the user button must be held during boot
(to bypass the stock uboot) or the internal uboot must be updated. To
allow for a better out-of-the-box experience, we just turn off the
watchdog.
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This section can be use to provide a cache coherent memory area via
rtems_cache_coherent_add_area().
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Specifically the beagleboard, beagleboard xM, beaglebone, beaglebone black.
More info on these targets: http://www.beagleboard.org/
This commit forms a basic BSP by combining Claas's work with
. new clock and irq code and definitions for
beagle targets (beagleboard and beaglebones), mostly
reused from the Minix codebase, thus making
irqs, ticks and non-polled console mode work too
. new timer code for ns timing with high timer resolution,
24MHz on the AM335X and 13MHz on the DM37XX
. select the console uart based on target at configure time
. removing all the lpc32xx-specific macros and code and
other unused code and definitions that the beagle bsp
was based on
. re-using some standard functions instead of lpc32xx versions
. fixed some whitespace problem in preinstall.am
. fixed some compile warnings
. configure MMU: set 1MB sections directly in the TTBR,
just to show the difference between cacheable RAM and
non-cacheable device memory and invalid ranges; this lets us
turn on caches and not rely on boot loader MMU configuration.
Verified to work when MMU is initially either on or off when
RTEMS gets control.
Thanks for testing, commentary, improvements and fixes to Chris Johns,
Brandon Matthews, Matt Carberry, Romain Bornet, AZ technology and others.
Signed-Off-By: Ben Gras <beng@shrike-systems.com>
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Coding done in course of GSoC2012.
Commit edited to be brought up-to-date with mainline by
Ben Gras <beng@shrike-systems.com>.
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