| Commit message (Collapse) | Author | Age | Files | Lines |
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. added a README to pwm
. added select_pwmss() to select pwmss-generic registers, as opposed
to PWM-specific registers
. added pwmss_clock_en_status(), beagle_pwmss_is_running() and pwmss_tb_clock_check()
. other API improvements
. style improvements
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This patch adapts the previously added Beaglebone PWM code from BBBIO to RTEMS.
This work was done in the context of the Google Summer of Code 2016, and further
patches will follow to improve the code quality and documentation.
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This patch adds the PWM driver code for the Beaglebone Black from BBBIO:
https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.c
This commit is for tracking purposes only; the next commit will adapt the code for
RTEMS.
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flush_data_cache uses R0 directly but doesn't list it as a clobbered
register. Compiling with -O3 made this code break, since the function
that calls flush_data_cache already uses r0.
closes #2416.
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GPIO Driver Development for BeagleBone Black based on the generic GPIO API
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unused and poorly named (no prefix) and colliding with sp68.
Closes #2302.
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Specifically the beagleboard, beagleboard xM, beaglebone, beaglebone black.
More info on these targets: http://www.beagleboard.org/
This commit forms a basic BSP by combining Claas's work with
. new clock and irq code and definitions for
beagle targets (beagleboard and beaglebones), mostly
reused from the Minix codebase, thus making
irqs, ticks and non-polled console mode work too
. new timer code for ns timing with high timer resolution,
24MHz on the AM335X and 13MHz on the DM37XX
. select the console uart based on target at configure time
. removing all the lpc32xx-specific macros and code and
other unused code and definitions that the beagle bsp
was based on
. re-using some standard functions instead of lpc32xx versions
. fixed some whitespace problem in preinstall.am
. fixed some compile warnings
. configure MMU: set 1MB sections directly in the TTBR,
just to show the difference between cacheable RAM and
non-cacheable device memory and invalid ranges; this lets us
turn on caches and not rely on boot loader MMU configuration.
Verified to work when MMU is initially either on or off when
RTEMS gets control.
Thanks for testing, commentary, improvements and fixes to Chris Johns,
Brandon Matthews, Matt Carberry, Romain Bornet, AZ technology and others.
Signed-Off-By: Ben Gras <beng@shrike-systems.com>
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Coding done in course of GSoC2012.
Commit edited to be brought up-to-date with mainline by
Ben Gras <beng@shrike-systems.com>.
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