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* libbsp/arm: Fix ARM BSPs missing the bsp_translation_table_end symbol.Chris Johns2016-10-021-0/+1
| | | | Closes #2775.
* Multiple bsp_specs: Change *(old_endfile) to %(old_endfile)Joel Sherrill2015-05-211-1/+1
| | | | | | Fix typo. closes 2345.
* bsp/altera-cyclone-v: Add RTC driverThomas Volgmann2015-04-101-144/+622
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* bsp/altera-cyclone-v: Fix define usageSebastian Huber2015-04-021-1/+1
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* bsp/altera-cyclone-v: TypoSebastian Huber2015-03-251-3/+3
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* bsp/altera-cyclone-v: Use proper free functionSebastian Huber2015-01-231-1/+1
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* Update bug report URLSebastian Huber2014-12-051-1/+1
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* bsps/arm: Add .nocache sectionSebastian Huber2014-11-279-182/+11
| | | | | This section can be use to provide a cache coherent memory area via rtems_cache_coherent_add_area().
* bsps/arm: Enable L2C for Cortex-A9 MPCore BSPsSebastian Huber2014-11-203-47/+7
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* bsps/arm: L2C 310 add compile time checksSebastian Huber2014-11-201-2/+4
| | | | Simplify initialization. Replace some assert() with fatal errors.
* bsps/arm: L2C 310 rename BSP_ARM_L2CC_BASESebastian Huber2014-11-201-1/+1
| | | | Rename BSP_ARM_L2CC_BASE to BSP_ARM_L2C_310_BASE.
* libchip/serial: Add alternative NS16550 driverSebastian Huber2014-10-072-95/+71
| | | | Use the Termios device API.
* bsps: Fix build errorSebastian Huber2014-09-182-5/+0
| | | | Fix build error introduced in f535fe5311978af53635c2da8e5cb10ef9d78802.
* bsps/arm: Add a9mpcore_clock_initialize_early()Sebastian Huber2014-09-101-0/+2
| | | | | This is necessary to use the CPU counter converter even in case no clock driver is present, e.g. in tmcontext01.
* bsp/altera-cyclone-v: Add BSP_USE_UART_INTERRUPTSSebastian Huber2014-09-102-3/+12
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* bsps/arm: Do not build unused fileSebastian Huber2014-09-081-1/+0
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* Regenerate all preinstall.am files.Chris Johns2014-08-291-3/+3
| | | | | With this patch the preinstall.am files are in a set order and not dependent on now perl implements a hash.
* Regenerate all preinstall.am files.Joel Sherrill2014-08-281-7/+7
| | | | | Apparently, at some point automake output changed and these were not updated.
* preinstall: Regenerated files differ from the repo.Chris Johns2014-08-281-6/+6
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* bsp/altera-cyclone-v: Add DMA support hwlib filesSebastian Huber2014-08-2617-7/+21297
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* bsp/altera-cyclone-v: Update to hwlib 13.1Sebastian Huber2014-08-2616-3841/+8786
| | | | This version is distributed with SoC EDS 14.0.0.200.
* libchip/dwmac: Make PHY address user configurableChristian Mauderer2014-08-221-0/+28
| | | | | | This patch allows the user to configure the PHY address for the DWMAC driver by giving a pointer to a dwmac_user_cfg structure to network stack via rtems_bsdnet_ifconfig::drv_ctrl.
* bsp/altera-cyclone-v: Add RTC driver.Christian Mauderer2014-08-114-4/+381
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* bsp/altera-cyclone-v: Add a simple I2C driver.Christian Mauderer2014-08-1111-7/+10389
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* bsp/altera-cyclone-v: Add socal from hwlib.Christian Mauderer2014-08-112-2/+60
| | | | Some of the headers from the hwlib need the files from the socal subdirectory.
* bsp/altera-cyclone-v: Move MMU configuration tableSebastian Huber2014-07-013-20/+37
| | | | This makes it possible to use application specific version.
* bsp/altera-cyclone-v: Enable unified L2 cacheSebastian Huber2014-06-062-1/+12
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* bsp/altera-cyclone-v: Move SMP supportSebastian Huber2014-06-063-54/+94
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* bsp/altera-cyclone-v: Simplify start hooksSebastian Huber2014-06-061-120/+25
| | | | Use arm_a9mpcore_start_hook_0(). The L2 cache is now disabled.
* bsp/altera-cyclone-v: Change default baudSebastian Huber2014-06-061-1/+1
| | | | Use value for standard U-Boot.
* bsp/altera-cyclone-v: Use NOLOAD for nocache secSebastian Huber2014-06-061-1/+1
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* bsp/altera-cyclone-v: Simplify MMU config tableSebastian Huber2014-06-061-2/+1
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* bsps/arm: Define ARM_CP15_TEXT_SECTIONSebastian Huber2014-06-061-1/+3
| | | | | Define ARM_CP15_TEXT_SECTION to BSP_START_TEXT_SECTION so that the start code is in the right section.
* bsp/altera-cyclone-v: CleanupRalf Kirchner2014-05-281-3/+3
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* bsp/altera-cyclone-v: Reduce size of nocache heapRalf Kirchner2014-05-282-4/+4
| | | | Network mbufs and clusters now are cached. Thus the nocache heap can get reduced to 1 MByte.
* bsp/altera-cyclone-v: Cache mbufs and clustersRalf Kirchner2014-05-281-12/+0
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* bsp/altera-cyclone-v: Enable L2 cache for network driverRalf Kirchner2014-05-281-1/+14
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* bsp/altera-vyclone-v: Broadcast cache maintenancesRalf Kirchner2014-05-281-3/+3
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* bsp/altera-caclone-v: Early printk supportRalf Kirchner2014-05-121-24/+4
| | | | Make sure printk can work early during BSP startup.
* bsp/altera-cyclone-v: Move mbufs and network clusters to uncached RAMRalf Kirchner2014-04-301-0/+12
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* bsp/altera-cyclone-v: Increase size of nocache region and nocache heapRalf Kirchner2014-04-302-3/+3
| | | | Increase size of nocache heap in order to be able to move mbufs and clusters of the network driver to uncached RAM
* bsp/altera-cyclone-v: CleanupRalf Kirchner2014-04-171-2/+0
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* bsp/altera-cyclone-v: Change console baud rateRalf Kirchner2014-04-171-1/+1
| | | | | | The baud rate of the altera cyclone-V U-Boot can not be changed at the u-Boot console prompt. Thus we use the same baud rate as the U-Boot for the BSP.
* rtems: Rename rtems_smp_get_current_processor()Sebastian Huber2014-04-111-1/+1
| | | | | | | Rename rtems_smp_get_current_processor() in rtems_get_current_processor(). Make rtems_get_current_processor() a function in uni-processor configurations to enable ABI compatibility with SMP configurations.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-217-7/+7
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* bsp/altera-cyclone-v: Made hwlib compile cleanRalf Kirchner2014-03-133-281/+6
| | | | Made Alteras hwlib compile clean within the RTEMS build system
* bsp/altera-cyclone-v: Add Alteras hwlibRalf Kirchner2014-03-1323-0/+71250
| | | | Add files from Alteras hwlib
* bsp/altera-cyclone-v: New BSPRalf Kirchner2014-03-1321-0/+2542
Implemented so far: - nocache heap for uncached RAM - basic timer - level 1 cache handling for arm cache controller in arm-cache-l1.h - level 2 L2C-310 cache controller - MMU - DWMAC 1000 ethernet controller - basic errata handling - smp startup for second core
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