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* Change all references of rtems.com to rtems.org.Chris Johns2014-03-213-3/+3
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* bsp/altera-cyclone-v: New BSPRalf Kirchner2014-03-134-0/+185
Implemented so far: - nocache heap for uncached RAM - basic timer - level 1 cache handling for arm cache controller in arm-cache-l1.h - level 2 L2C-310 cache controller - MMU - DWMAC 1000 ethernet controller - basic errata handling - smp startup for second core