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path: root/c/src/lib/libbsp/arm/altera-cyclone-v/include/bsp.h (follow)
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* bsps/arm: L2C 310 rename BSP_ARM_L2CC_BASESebastian Huber2014-11-201-1/+1
| | | | Rename BSP_ARM_L2CC_BASE to BSP_ARM_L2C_310_BASE.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* bsp/altera-cyclone-v: New BSPRalf Kirchner2014-03-131-0/+65
Implemented so far: - nocache heap for uncached RAM - basic timer - level 1 cache handling for arm cache controller in arm-cache-l1.h - level 2 L2C-310 cache controller - MMU - DWMAC 1000 ethernet controller - basic errata handling - smp startup for second core