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* Patch rtems-rc-20000801-1-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-08-011-1/+1
| | | | that switches the sparc from targopts.h to cpuopts.h.
* Port of RTEMS to the ARM processor family by Eric ValetteJoel Sherrill2000-07-2715-0/+1771
| | | | | | <valette@crf.canon.fr> and Emmanuel Raguet <raguet@crf.canon.fr> of Canon CRF - Communication Dept. This port includes a basic BSP that is sufficient to link hello world.
* Port of RTEMS to the Texas Instruments C3x/C4x DSP families includingJoel Sherrill2000-07-2622-3/+69
| | | | | | | | | | | a BSP (c4xsim) supporting the simulator included with gdb. This port was done by Joel Sherrill and Jennifer Averett of OAR Corporation. Also included with this port is a space/time optimization to eliminate FP context switch management on CPUs without hardware or software FP. An issue with this port was that sizeof(unsigned32) = sizeof(unsigned8) on this CPU. This required addressing alignment checks and assumptions as well as fixing code that assumed sizeof(unsigned32) == 4.
* Patch rtems-rc-20000713-1-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-07-251-2/+0
| | | | that removes an unnecessary inclusion of @RTEMS_BSP@.cfg.
* Forgot to remove these when code moved.Joel Sherrill2000-07-2516-4955/+0
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* Use bitwise and not cast to unsigned16 to remove upper bits.Joel Sherrill2000-07-242-2/+6
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* Make _ISR_Dispatch global.Joel Sherrill2000-07-171-0/+1
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* Update from Philip Quaife <rtemsdev@qs.co.nz> that was hand-merged.Joel Sherrill2000-07-172-34/+75
| | | | | | | | | | This update addresses the following: + the ISR enable/disable/flash macros now work with old gcc versions. + the UI CCR bits are now masked since other example code did so + _ISR_Dispatch disables interrupts during call setup Together these removed the instabilities he was seeing.
* Patch rtems-rc-20000713-1-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-07-131-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | that is yet another multilib-related structual cleanup patch: Changes: * Make RTEMS_TEST_NO_PAUSE a tests/ subpackage specific option. - Remove RTEMS_TEST_NO_PAUSE from custom/*.cfg, targopts.h and cpuopts.h. - Add autoconf macros RTEMS_*_RTEMS_TEST_NO_PAUSE (aclocal/rtems-test-no-pause.m4). - Add RTEMS_*_RTEMS_TEST_NO_PAUSE support to sptests/configure.ins and tmtests/configure.in. These are the only subdirectories which currently apply RTEMS_TEST_NO_PAUSE. - Add autoconf-DEFS support to all test subpackages' configure.ins below tests/. I.e. AC_DEFINES now get explicitly propagated as preprocessor defines into Makefiles, cf. AM_CPPFLAGS in tests/*/*.am, instead of using a global config-files. - Remove NDEBUG from custom/*.cfg. * AC_DEFINE POSIX_API, ITRON_API and MULTIPROCESSING in exec/configure.in, only. - All other sources now should relay on the values from cpuopts.h and should not define them themselves. - Several related changes to many configure.ins * Bug-fixes to RTEMS_*_RTEMS_DEBUG macros (Actually workarounds to quoting bugs in autoconf). Notes: * This patch is rather immature and only tested for a small subset of BSPs (requires the tests to be enabled and therefore takes an tremendous amount of disc space and time.) * The patches to *cfg were generated by a script. Expect file formating changes :)
* Removed no cpu references.Joel Sherrill2000-07-1113-15/+15
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* Reworked score/cpu/sparc so it can be safely compiled multilib. AllJoel Sherrill2000-07-1112-660/+31
| | | | | | routines and structures that require CPU model specific information are now in libcpu. This primarily required moving erc32 specific information from score/cpu files to libcpu/sparc and the erc32 BSP.
* Added Hitachi H8/300 to the list of CPUs that should be OK withJoel Sherrill2000-07-111-0/+1
| | | | using cpuopts.h and not targopts.h.
* Reworked score/cpu/i960 so it can be safely compiled multilib. AllJoel Sherrill2000-07-116-851/+31
| | | | | | | routines and structures that require CPU model specific information are now in libcpu. This required significant rework of the score/cpu header files and the creation of multiple header files and subdirectories in libcpu/i960.
* Patch rtems-rc-20000711-1-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-07-115-6/+13
| | | | | | | | | that decouples exec/ for the sh, m68k and i960 from targopts.h. NOTE: The change to system.h is a hack to enable cpuopts.h for some targets, but keep using targopts.h for others - I know it does *not* work for sparc, mips, i386 and ppc. This will have to be addressed as work continues on multilibing.
* Patch rtems-rc-20000709-1.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-07-103-53/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | that addresses aspects of the targopts.h multilib related issues. Changes: * Move targopts.h to libbsp/include, because the current targopts.h actually is a per-BSP-header and therefore can not stay below exec/. * Introduce an autoheader generated header file (exec/score/include/rtems/score/cpuopts.h), which shall take per-cpu configuration options only. * Move all autoconf-detectable/configure specified per-cpu option-defines from targopts.h to cpuopts.h. * Add Makefiles to the libbsp/shared directory hierarchy. Notes: * The new per-bsp targopts.h in libbsp includes the per-cpu cpuopts.h. This way, the new targopts.h is kept backward compatible to the old targopts.h and existing BSPs which (carelessly) include targopts.h (i386, ppc) should be kept working when using the multilib-disabled configuration scheme. * cpuopts.h is not yet complete, because the per-BSP make-targopts rules from custom/<BSP>.cfg files can not be applied to files below exec/ when building multilibs. * All files below exec/ should not include targopts.h anymore, but should include cpuopts.h instead. However, eliminating inclusion of targopts.h currently triggers further structural / header file inclusion related issues, because several ports apply BSP or CPU_MODEL specific defines from targopts.h below exec/
* Patch rtems-rc-20000708-1.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-07-1013-39/+0
| | | | | | | | | | | | | | | | | that is another small step toward multilibs: Changes: * Eliminate RTEMS_CHECK_CUSTOM_BSP from all configure.ins below exec/ * Add RTEMS_CHECK_CUSTOM_BSP to the multilib-disabled branch in RTEMS_ENV_RTEMSCPU to preserve the old per-BSP building scheme functional. Notes: * --enable-multilibs is still non-functional * This patch should not have any influence on the old building scheme (--disable-multilib should silently fall back to the old building scheme). * running ./bootstrap is required after applying the patch
* Moved old_exception_processing and new_exception_processing directoriesJoel Sherrill2000-07-074-28/+10
| | | | | | from score/cpu to libcpu because the determination of which to use is based on RTEMS_CPU_MODEL. Thus it can not be determined based solely on multilib information.
* Moved __RTEMS_APPLICATION__ conditional to include the use of theJoel Sherrill2000-07-071-1/+1
| | | | | static inline routine _CORE_mutex_Seize_interrupt_trylock since static routines are not included when in an application.
* Patch rtems-rc-20000705-3.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-07-0614-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | that is a somewhat experimental, multilib-related patch: Changes: * Use RTEMS_ENV_RTEMSCPU instead of RTEMS_ENV_RTEMSBSP in configure.ins below exec/. At the moment, RTEMS_ENV_RTEMSCPU is more or less an optical change to emphasize that these subdirectories shall not depend on RTEMS_BSP than a real behavioral change. * Add AC_DEFINE_* to several aclocal/*.m4 macros to prepare autoheader/autoconf generated targopts.h and similiar configuration headers. * c/src/configure.in: remove exec from cfg_subdirs if multilibs are enabled (c/src is build per bsp, exec shall be build per cpu in c/ or from the toplevel in future, when multilibs are enabled.) Notes: * This patch should not have any impact on the current building scheme. * --enable-multilib still does not work. * running bootstrap from the toplevel directory is required. CVS: ---------------------------------------------------------------------- CVS: Enter Log. Lines beginning with `CVS:' are removed automatically CVS: CVS: Committing in . CVS: CVS: Modified Files: CVS: c/src/tests/libtests/termios/init.c CVS: ----------------------------------------------------------------------
* Added missing #endif's.Joel Sherrill2000-07-062-3/+0
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* Corrected call to _CORE_mutex_Seize_interrupt_blocking.Joel Sherrill2000-07-061-2/+5
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* Reimplemented _Core_MUTEX_Seize to return with interrupts disabledJoel Sherrill2000-07-062-7/+119
| | | | if the mutex is successfully obtained.
* Added _CORE_semaphore_Seize_isr_disable.Joel Sherrill2000-07-061-0/+56
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* Added _Objects_Get_isr_disable prototype and added numerous comments.Joel Sherrill2000-07-061-7/+18
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* Removed unnecessary parentheses.Joel Sherrill2000-07-061-4/+4
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* Added objjectgetbyisr.cJoel Sherrill2000-07-061-2/+3
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* The code that attempts to obtain a mutex has now been inlined. TheJoel Sherrill2000-07-061-83/+7
| | | | code remaining here now only blocks.
* Directly index local table to avoid error check.Joel Sherrill2000-07-063-12/+10
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* New file. Convert ID to pointer and return with interrupts -- notJoel Sherrill2000-07-061-0/+83
| | | | dispatching -- disabled.
* Format of return line changed.Joel Sherrill2000-07-061-3/+3
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* Interrupt stack is allocated in _ISR_Handler_initialization notJoel Sherrill2000-07-0310-10/+10
| | | | _Interrupt_Manager_initialization.
* Added blocked_count field to allow for optimizations.Joel Sherrill2000-07-032-2/+4
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* Changed extra_system_initialization_stack to extra_mpci_receive_server_stackJoel Sherrill2000-07-031-1/+1
| | | | to be consistent with other ports.
* This is the initial addition of the port of RTEMS to theJoel Sherrill2000-06-2916-0/+2025
| | | | | | | | | | | | | Hitachi H8 family. This port was done by Philip Quaife <philip@qs.co.nz> of Q Solutions and sponsored by Comnet Technologies Ltd. The port was done based on RTEMS 3.5.1 to a Hitach H8300H. The port was updated to RTEMS 4.5 style Makefiles/configure by Joel Sherrill <joel@OARcorp.com>. While doing this Joel added support for the h8300-rtems to binutils, gcc, newlib, and gdb. NOTE: Philip submitted a BSP for a Hitachi evaluation board which is being merged as a separate entity.
* Added RTEMS_CPU_HAS_16_BIT_ADDRESSES constant to disable codeJoel Sherrill2000-06-291-0/+4
| | | | | | | | that breaks when the target has 16 bit address space. One of the H8 multilibs is a 16-bit address space CPU. When a real attempt is made to support this CPU model, the code that assumes an address is 32 bits will have to change. This constant is probably not flagging all impacted code.
* Remove pragma align 4Joel Sherrill2000-06-151-2/+0
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* Patch rtems-rc-20000615-1-cvs.diff from Ralf CorsepiusJoel Sherrill2000-06-151-1/+1
| | | | <corsepiu@faw.uni-ulm.de> to fix a bad file reference.
* Patch rtems-rc-20000614-sh.tar.gz from Ralf CorsepiusJoel Sherrill2000-06-1410-1824/+14
| | | | | | | | | | | | | | | | | | | | | <corsepiu@faw.uni-ulm.de> that migrates the SH port to multilib'ing. This patch involved moving a number of files in the CVS repository, adding new files, and deleting files from their previous location. Ralf gave good instructions (not repeated here) and here are his notes: Note 1: In this version, I did not change the installation points of the headers which are moved inside of the source-tree. This is a temporary hack for not breaking compatibility with 4.5 based BSPs, but will probably not last once having real multilibs (We would have include file conflicts when several BSPs/CPU_MODELS share a common installation prefix). Note 2: I hope not to have broken too much, but I would not be astonished if something goes wrong. Note 3: There are more patches to come :)
* Moved PowerPC cache management code to libcpu. Also compiledJoel Sherrill2000-06-142-302/+0
| | | | | | mpc8xx libcpu support for the first time and remove includes of bsp.h, references to BSP_Configuration, and Cpu_table. All of these can be obtained directly from RTEMS now.
* Thread iterator and libgjc support submitted too early.Joel Sherrill2000-06-145-215/+9
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* Added crude i960ka support.Joel Sherrill2000-06-133-6/+38
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* Moved i386 and m68k cache management code to libcpu. EverythingJoel Sherrill2000-06-132-306/+0
| | | | | | now is an implementation of the prototypes in rtems/rtems/cache.h. The libcpu/i386/wrapup directory is no longer needed. The PowerPC needs this done to it.
* Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine GauthierJoel Sherrill2000-06-121-61/+0
| | | | | | | | | | | | | | | <charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart <Darlene.Stewart@nrc.ca> to add support for a number of very significant things: + BSPs for many variations on the Motorola MBX8xx board series + Cache Manager including initial support for m68040 and PowerPC + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use same code base. + Rework of eth_comm BSP to utiltize above. John reports this works on the 821 and 860.
* Fixed so hppa1.1 compiles with only problems in simhppa BSP.Joel Sherrill2000-06-121-3/+13
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* Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine GauthierJoel Sherrill2000-06-1214-23/+928
| | | | | | | | | | | | | | | <charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart <Darlene.Stewart@nrc.ca> to add support for a number of very significant things: + BSPs for many variations on the Motorola MBX8xx board series + Cache Manager including initial support for m68040 and PowerPC + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use same code base. + Rework of eth_comm BSP to utiltize above. John reports this works on the 821 and 860
* Works on Solaris and Linux.Joel Sherrill2000-06-121-8/+6
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* Merged from 4.5.0-beta3aJoel Sherrill2000-06-1269-232/+707
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* Patch rtems-rc-4.5.0-13-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>.Joel Sherrill2000-04-1322-0/+88
| | | | adds .cvsignore.
* Patch rtems-rc-4.5.0-13-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>.Joel Sherrill2000-04-1327-0/+142
| | | | adds .cvsignore.
* Added routines to get and set C3x IOF register. The code is conditionallyJoel Sherrill2000-03-011-13/+71
| | | | compiled and there is no comparable code for the C4x.
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