| Commit message (Collapse) | Author | Age | Files | Lines |
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This modification is part of the submitted modifications necessary to
support the IBM PPC405 family. This submission was reviewed by
Thomas Doerfler <Thomas.Doerfler@imd-systems.de> who ensured it did
not negatively impact the ppc403 BSPs. The submission and tracking
process was captured as PR50.
* shared/asm.h, shared/ppc.h: Added PPC405 support.
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* shared/ppc.h: Added mpc8260 support.
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* cpu.c: Fix #ifdefs, add missing #endif.
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* shared/ppctypes.h: Fixed typo.
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* .cvsignore: Add autom4te.cache for autoconf > 2.52.
* configure.in: Remove.
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* .cvsignore: Add autom4te.cache for autoconf > 2.52.
* configure.in: Remove.
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* asm.h, cpu.c, rtems.c, rtems/score/cpu.h, rtems/score/sh.h,
rtems/score/sh_io.h, rtems/score/shtypes.h: Consistency changes
and made sure there were no includes from the libcpu tree.
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* cpu.c, rtems/score/cpu.h, rtems/score/sh.h: Modified to
support SH4. Reviewed by Ralf Corsepius <corsepiu@faw.uni-ulm.de>
who did the original SH port.
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* cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
compilation block with (CPU_HARDWARE_FP == FALSE). Reported by
Wayne Bullaughey <wayne@wmi.com>.
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* .cvsignore: Add autom4te.cache for autoconf > 2.52.
* configure.in: Remove.
* configure.ac: New file, generated from configure.in by autoupdate.
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* .cvsignore: Add autom4te.cache for autoconf > 2.52.
* configure.in: Remove.
* configure.ac: New file, generated from configure.in by autoupdate.
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* .cvsignore: Add autom4te.cache for autoconf > 2.52.
* configure.in: Remove.
* configure.ac: New file, generated from configure.in by autoupdate.
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* cpu_asm.S: Small patch to fix a bug in the rtems sparc port. The
bug has been there all the time, but only hits the leon bsp since the
leon cpu has a 5-stage pipeline (erc32 has 4 stages).
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* cpu_asm.S: Small patch to fix a bug in the rtems sparc port. The
bug has been there all the time, but only hits the leon bsp since the
leon cpu has a 5-stage pipeline (erc32 has 4 stages).
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* rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
* Makefile.am: Use 'PREINSTALL_FILES ='.
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* shared/Makefile.am: Use 'PREINSTALL_FILES ='.
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* rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
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* cpu.c (_CPU_ISR_install_vector): Corrected interrupt range
checking which was SH1 specific. It didn't work for SH2 (has more
interrupt sources).
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* cpu_asm.S: This patch was co-developed with Eric Norum
<eric.norum@usask.ca>. It closes a one instruction window
on some m68k CPU cores. It fixes symptoms seen as:
1) No more `interrupt handler invoked twice for
a single interrupt'.
2) No more `lockup when mc68360 CPM and PIT interrupts
are at different levels'.
It does insert a little more overhead on machines without hardware
interrupt stacks but correctness has a price.
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* cpu.c: Fixed typo.
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* rtems/score/mips.h: Added constants for MIPS exception numbers.
All exceptions should be given low numbers and thus can be installed
and processed in a uniform manner. Variances between various MIPS
ISA levels were not accounted for.
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* rtems/score/mips.h: Added constants for MIPS exception numbers.
All exceptions should be given low numbers and thus can be installed
and processed in a uniform manner. Variances between various MIPS
ISA levels were not accounted for.
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* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
* cpu_asm.S: Now works on Mongoose-V. Missed in previous patch.
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* rtems/score/cpu.h: Add the interrupt stack structure and enhance
the context initialization to account for floating point tasks.
* rtems/score/mips.h: Added the routines mips_set_cause(),
mips_get_fcr31(), and mips_set_fcr31().
* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
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* rtems/score/cpu.h: Remove #undef __STRICT_ANSI__.
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* cpu_asm.S: Merged patches from Gregory Menke
<Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
stack usage and include nops in the delay slots.
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* cpu_asm.S: Added code to save and restore SR and EPC to
properly support nested interrupts. Note that the ISR
(not RTEMS) enables interrupts allowing the nesting to occur.
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* cpu.c: Removed duplicate declaration for _ISR_Vector_table.
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* cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
Removed unused variable _CPU_Thread_dispatch_pointer
and cleaned numerous comments.
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* cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
Also reimplemented some assembly routines in C further reducing
the amount of assembly and increasing maintainability.
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* Makefile.am, rtems/score/Makefile.am:
Apply include_*HEADERS instead of H_FILES.
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* cpu.c, rtems/score/cpu.h: Bug report from Peter Mueller
<peter.o.mueller@gmx.de> because of not correcting for the ISR
vector table now being allocated from the workspace.
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* rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
register constraints from "general" to "register".
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* cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
to make it easier to conditionalize the code for various ISA levels.
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* idtcpu.h: Commented out definition of "wait". It was stupid to
use such a common word as a macro.
* rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
* rtems/score/mips.h: Added include of <idtcpu.h>.
* rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Modify to properly dereference _ISR_Vector_table
now that it is dynamically allocated.
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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Modify to properly dereference _ISR_Vector_table
now that it is dynamically allocated.
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* ChangeLog: Removed duplicate entry.
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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
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* cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
Previous code resulting in the interrupted immediately returning
to the caller of the routine it was inside.
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* cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
because it has not been allocated yet.
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* cpu.c: Do not read or write raw interrupt vector table if
we are on a CPU that does not have a %vbr register and the
BSP is configured as having the table in ROM.
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* cpu.c: Removed duplicate declaration for _ISR_Vector_table.
* cpu_asm.S: Removed assembly language to vector ISR handler
on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP.
* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
longer a constant -- get the real value from libcpu.
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* cpu_asm.h: Removed.
* Makefile.am: Remove cpu_asm.h.
* rtems/score/mips64orion.h: Renamed mips.h.
* rtems/score/mips.h: New file, formerly mips64orion.h.
Header rewritten.
(mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
mips_disable_in_interrupt_mask): New macros.
* rtems/score/Makefile.am: Reflect renaming mips64orion.h.
* asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
few defines that were in <cpu_asm.h>.
* cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
MIPS ISA 3 is still in assembly for now.
(_CPU_Thread_Idle_body): Rewrote in C.
* cpu_asm.S: Rewrote file header.
(FRAME,ENDFRAME) now in asm.h.
(_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
(_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
(_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
leaves other bits in SR alone on task switch.
(mips_enable_interrupts,mips_disable_interrupts,
mips_enable_global_interrupts,mips_disable_global_interrupts,
disable_int, enable_int): Removed.
(mips_get_sr): Rewritten as C macro.
(_CPU_Thread_Idle_body): Rewritten in C.
(init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
placed in libcpu.
(exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
to libcpu/mips/shared/interrupts.
(general): Cleaned up comment blocks and #if 0 areas.
* idtcpu.h: Made ifdef report an error.
* iregdef.h: Removed warning.
* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
number defined by libcpu.
(_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
to access SR.
(_CPU_ISR_Set_level): Rewritten as macro for ISA I.
(_CPU_Context_Initialize): Honor ISR level in task initialization.
(_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
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* cpu.c: Added include of <rtems/rtems/cache.h> to eliminate warning.
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* rtems/score/cpu.h: When mips ISA level is 1, registers in the
context should be 32 not 64 bits.
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