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* 2001-10-12 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-10-129-25/+59
| | | | | | * asm.h, cpu.c, rtems.c, rtems/score/cpu.h, rtems/score/sh.h, rtems/score/sh_io.h, rtems/score/shtypes.h: Consistency changes and made sure there were no includes from the libcpu tree.
* 2001-10-12 Alexandra Kossovsky <sasha@oktet.ru>Joel Sherrill2001-10-124-16/+146
| | | | | | * cpu.c, rtems/score/cpu.h, rtems/score/sh.h: Modified to support SH4. Reviewed by Ralf Corsepius <corsepiu@faw.uni-ulm.de> who did the original SH port.
* 2001-10-12 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-10-122-2/+8
| | | | | | * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional compilation block with (CPU_HARDWARE_FP == FALSE). Reported by Wayne Bullaughey <wayne@wmi.com>.
* 2001-10-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-10-124-129/+0
| | | | | | * .cvsignore: Add autom4te.cache for autoconf > 2.52. * configure.in: Remove. * configure.ac: New file, generated from configure.in by autoupdate.
* 2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-10-118-0/+28
| | | | | | * .cvsignore: Add autom4te.cache for autoconf > 2.52. * configure.in: Remove. * configure.ac: New file, generated from configure.in by autoupdate.
* 2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-10-1139-104/+208
| | | | | | * .cvsignore: Add autom4te.cache for autoconf > 2.52. * configure.in: Remove. * configure.ac: New file, generated from configure.in by autoupdate.
* 2001-09-27 Jiri Gaisler <jiri@gaisler.com>Joel Sherrill2001-09-281-0/+7
| | | | | | * cpu_asm.S: Small patch to fix a bug in the rtems sparc port. The bug has been there all the time, but only hits the leon bsp since the leon cpu has a 5-stage pipeline (erc32 has 4 stages).
* 2001-09-27 Jiri Gaisler <jiri@gaisler.com>Joel Sherrill2001-09-271-4/+4
| | | | | | * cpu_asm.S: Small patch to fix a bug in the rtems sparc port. The bug has been there all the time, but only hits the leon bsp since the leon cpu has a 5-stage pipeline (erc32 has 4 stages).
* 2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-09-2744-30/+105
| | | | | * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. * Makefile.am: Use 'PREINSTALL_FILES ='.
* 2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-09-272-1/+5
| | | | * shared/Makefile.am: Use 'PREINSTALL_FILES ='.
* 2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-09-272-1/+5
| | | | * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
* 2001-07-25 Radzislaw Galler <rgaller@et.put.poznan.pl>Joel Sherrill2001-08-162-1/+10
| | | | | | * cpu.c (_CPU_ISR_install_vector): Corrected interrupt range checking which was SH1 specific. It didn't work for SH2 (has more interrupt sources).
* 2001-08-09 Chris Johns <ccj@acm.org>Joel Sherrill2001-08-092-63/+48
| | | | | | | | | | | | * cpu_asm.S: This patch was co-developed with Eric Norum <eric.norum@usask.ca>. It closes a one instruction window on some m68k CPU cores. It fixes symptoms seen as: 1) No more `interrupt handler invoked twice for a single interrupt'. 2) No more `lockup when mc68360 CPM and PIT interrupts are at different levels'. It does insert a little more overhead on machines without hardware interrupt stacks but correctness has a price.
* 2001-07-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-07-032-1/+5
| | | | * cpu.c: Fixed typo.
* 2000-05-24 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-05-241-7/+38
| | | | | | | * rtems/score/mips.h: Added constants for MIPS exception numbers. All exceptions should be given low numbers and thus can be installed and processed in a uniform manner. Variances between various MIPS ISA levels were not accounted for.
* 2000-05-24 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-05-241-0/+7
| | | | | | | | * rtems/score/mips.h: Added constants for MIPS exception numbers. All exceptions should be given low numbers and thus can be installed and processed in a uniform manner. Variances between various MIPS ISA levels were not accounted for.
* 2001-05-24 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2001-05-242-57/+157
| | | | | * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>. * cpu_asm.S: Now works on Mongoose-V. Missed in previous patch.
* 2001-05-22 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2001-05-223-21/+86
| | | | | | | | * rtems/score/cpu.h: Add the interrupt stack structure and enhance the context initialization to account for floating point tasks. * rtems/score/mips.h: Added the routines mips_set_cause(), mips_get_fcr31(), and mips_set_fcr31(). * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
* 2001-05-07 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-05-082-2/+4
| | | | * rtems/score/cpu.h: Remove #undef __STRICT_ANSI__.
* 2001-05-07 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-05-072-67/+95
| | | | | | * cpu_asm.S: Merged patches from Gregory Menke <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up stack usage and include nops in the delay slots.
* 2001-04-20 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-04-202-0/+15
| | | | | | * cpu_asm.S: Added code to save and restore SR and EPC to properly support nested interrupts. Note that the ISR (not RTEMS) enables interrupts allowing the nesting to occur.
* 2001-04-11 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-04-112-2/+4
| | | | * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
* 2001-03-14 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-03-146-96/+59
| | | | | | * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: Removed unused variable _CPU_Thread_dispatch_pointer and cleaned numerous comments.
* 2001-03-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-03-146-722/+405
| | | | | | | * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h: Merged MIPS1 and MIPS3 code reducing the number of lines of assembly. Also reimplemented some assembly routines in C further reducing the amount of assembly and increasing maintainability.
* 2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-02-0549-113/+191
| | | | | * Makefile.am, rtems/score/Makefile.am: Apply include_*HEADERS instead of H_FILES.
* 2001-01-25 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-253-6/+16
| | | | | | * cpu.c, rtems/score/cpu.h: Bug report from Peter Mueller <peter.o.mueller@gmx.de> because of not correcting for the ISR vector table now being allocated from the workspace.
* 2001-01-12 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-122-2/+7
| | | | | * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected register constraints from "general" to "register".
* 2001-01-09 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-094-6/+27
| | | | | * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants to make it easier to conditionalize the code for various ISA levels.
* 2001-01-08 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-084-3/+16
| | | | | | | | * idtcpu.h: Commented out definition of "wait". It was stupid to use such a common word as a macro. * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3. * rtems/score/mips.h: Added include of <idtcpu.h>. * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-0312-6/+92
| | | | * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-0312-7/+61
| | | | | | * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). * cpu_asm.S: Modify to properly dereference _ISR_Vector_table now that it is dynamically allocated.
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-033-7/+20
| | | | | * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-033-3/+13
| | | | | | | * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). * cpu_asm.S: Modify to properly dereference _ISR_Vector_table now that it is dynamically allocated.
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-031-4/+0
| | | | * ChangeLog: Removed duplicate entry.
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-031-0/+4
| | | | * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-036-0/+28
| | | | * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-032-0/+10
| | | | * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* 2000-12-19 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-192-1/+9
| | | | | | * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register. Previous code resulting in the interrupted immediately returning to the caller of the routine it was inside.
* 2000-12-19 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-192-11/+5
| | | | | * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here because it has not been allocated yet.
* 2000-12-19 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-192-1/+8
| | | | | | * cpu.c: Do not read or write raw interrupt vector table if we are on a CPU that does not have a %vbr register and the BSP is configured as having the table in ROM.
* 2000-12-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-134-82/+16
| | | | | | | | * cpu.c: Removed duplicate declaration for _ISR_Vector_table. * cpu_asm.S: Removed assembly language to vector ISR handler on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP. * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No longer a constant -- get the real value from libcpu.
* 2000-12-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-1312-713/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * cpu_asm.h: Removed. * Makefile.am: Remove cpu_asm.h. * rtems/score/mips64orion.h: Renamed mips.h. * rtems/score/mips.h: New file, formerly mips64orion.h. Header rewritten. (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask, mips_disable_in_interrupt_mask): New macros. * rtems/score/Makefile.am: Reflect renaming mips64orion.h. * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the few defines that were in <cpu_asm.h>. * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine. MIPS ISA 3 is still in assembly for now. (_CPU_Thread_Idle_body): Rewrote in C. * cpu_asm.S: Rewrote file header. (FRAME,ENDFRAME) now in asm.h. (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C. (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C. (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and leaves other bits in SR alone on task switch. (mips_enable_interrupts,mips_disable_interrupts, mips_enable_global_interrupts,mips_disable_global_interrupts, disable_int, enable_int): Removed. (mips_get_sr): Rewritten as C macro. (_CPU_Thread_Idle_body): Rewritten in C. (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and placed in libcpu. (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved to libcpu/mips/shared/interrupts. (general): Cleaned up comment blocks and #if 0 areas. * idtcpu.h: Made ifdef report an error. * iregdef.h: Removed warning. * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable number defined by libcpu. (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines to access SR. (_CPU_ISR_Set_level): Rewritten as macro for ISA I. (_CPU_Context_Initialize): Honor ISR level in task initialization. (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
* 2000-12-06 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-062-0/+5
| | | | * cpu.c: Added include of <rtems/rtems/cache.h> to eliminate warning.
* 2000-12-06 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-062-0/+21
| | | | | * rtems/score/cpu.h: When mips ISA level is 1, registers in the context should be 32 not 64 bits.
* 2000-11-30 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-11-302-2/+14
| | | | | | * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to correct name of _CPU_Context_switch_restore. Added dummy version of exc_utlb_code() so applications would link.
* 2000-11-21 Jiri Gaisler <jgais@ws.estec.esa.nl>Joel Sherrill2000-11-212-3/+14
| | | | * cpu_asm.S: Fix for CPUs with FPU revision B or C.
* 2000-11-14 Jiri Gaisler <jgais@ws.estec.esa.nl>Joel Sherrill2000-11-153-1/+20
| | | | | | * cpu.c, rtems/cpu/sparc.h: Make floating point optional based on gcc arguments. Do not initialize FP context if there is no FPU. Flush instruction cache after installing RTEMS trap handler.
* 2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-11-0934-17/+85
| | | | * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
* 2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-11-0234-17/+85
| | | | * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
* 2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-10-2534-17/+102
| | | | | * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. Switch to GNU canonicalization.
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