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2002-07-22Remove, moved to cpukit.Ralf Corsepius1-1051/+0
2002-07-162002-07-16 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill1-2/+2
* cpu_asm.S: Added SR_IEO to context restore to fix isr disabled deadlock caused by interrupt arriving while dispatching.
2002-03-202002-03-20 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill1-0/+7
* cpu_asm.S: Now compiles on 4600 and 4650.
2002-03-152002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill1-1/+10
* cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug. * rtems/score/cpu.h: Fixed register numbering in comments and made interrupt enable/disable more robust.
2002-03-082002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill1-47/+143
* cpu_asm.S: Added support for the debug exception vector, cleaned up the exception processing & exception return stuff. Re-added EPC in the task context structure so the gdb stub will know where a thread is executing. Should've left it there in the first place... * idtcpu.h: Added support for the debug exception vector. * cpu.c: Added ___exceptionTaskStack to hold a pointer to the stack frame in an interrupt so context switch code can get the userspace EPC when scheduling. * rtems/score/cpu.h: Re-added EPC to the task context.
2002-03-012002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill1-95/+200
* cpu_asm.S: Fixed exception return address, modified FP context switch so FPU is properly enabled and also doesn't screw up the exception FP handling. * idtcpu.h: Added C0_TAR, the MIPS target address register used for returning from exceptions. * iregdef.h: Added R_TAR to the stack frame so the target address can be saved on a per-exception basis. The new entry is past the end of the frame gdb cares about, so doesn't affect gdb or cpu.h stuff. * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it to obtain FPU defines without systax errors generated by the C defintions. * cpu.c: Improved interrupt level saves & restores.
2002-02-052001-02-05 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-5/+83
* cpu_asm.S: Enhanced to save/restore more registers on exceptions. * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every register individually and document when it is saved. * idtcpu.h: Added constants for the coprocessor 1 registers revision and status.
2002-02-012001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill1-111/+158
* cpu.c: Enhancements and fixes for modifying the SR when changing the interrupt level. * cpu_asm.S: Fixed handling of FP enable bit so it is properly managed on a per-task basis, improved handling of interrupt levels, and made deferred FP contexts work on the MIPS. * rtems/score/cpu.h: Modified to support above changes.
2001-10-122001-10-12 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-2/+2
* cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional compilation block with (CPU_HARDWARE_FP == FALSE). Reported by Wayne Bullaughey <wayne@wmi.com>.
2001-05-242001-05-24 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill1-57/+152
* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>. * cpu_asm.S: Now works on Mongoose-V. Missed in previous patch.
2001-05-072001-05-07 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-67/+89
* cpu_asm.S: Merged patches from Gregory Menke <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up stack usage and include nops in the delay slots.
2001-04-202001-04-20 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-0/+9
* cpu_asm.S: Added code to save and restore SR and EPC to properly support nested interrupts. Note that the ISR (not RTEMS) enables interrupts allowing the nesting to occur.
2001-03-142001-03-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-635/+281
* cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h: Merged MIPS1 and MIPS3 code reducing the number of lines of assembly. Also reimplemented some assembly routines in C further reducing the amount of assembly and increasing maintainability.
2001-01-092001-01-09 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-5/+5
* cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants to make it easier to conditionalize the code for various ISA levels.
2001-01-032001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-6/+6
* rtems/score/cpu.h: Added _CPU_Initialize_vectors(). * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
2000-12-192000-12-19 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-1/+3
* cpu_asm.S (_ISR_Handler): Return to the address in the EPC register. Previous code resulting in the interrupted immediately returning to the caller of the routine it was inside.
2000-12-132000-12-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-79/+7
* cpu.c: Removed duplicate declaration for _ISR_Vector_table. * cpu_asm.S: Removed assembly language to vector ISR handler on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP. * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No longer a constant -- get the real value from libcpu.
2000-12-132000-12-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-451/+73
* cpu_asm.h: Removed. * Makefile.am: Remove cpu_asm.h. * rtems/score/mips64orion.h: Renamed mips.h. * rtems/score/mips.h: New file, formerly mips64orion.h. Header rewritten. (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask, mips_disable_in_interrupt_mask): New macros. * rtems/score/Makefile.am: Reflect renaming mips64orion.h. * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the few defines that were in <cpu_asm.h>. * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine. MIPS ISA 3 is still in assembly for now. (_CPU_Thread_Idle_body): Rewrote in C. * cpu_asm.S: Rewrote file header. (FRAME,ENDFRAME) now in asm.h. (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C. (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C. (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and leaves other bits in SR alone on task switch. (mips_enable_interrupts,mips_disable_interrupts, mips_enable_global_interrupts,mips_disable_global_interrupts, disable_int, enable_int): Removed. (mips_get_sr): Rewritten as C macro. (_CPU_Thread_Idle_body): Rewritten in C. (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and placed in libcpu. (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved to libcpu/mips/shared/interrupts. (general): Cleaned up comment blocks and #if 0 areas. * idtcpu.h: Made ifdef report an error. * iregdef.h: Removed warning. * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable number defined by libcpu. (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines to access SR. (_CPU_ISR_Set_level): Rewritten as macro for ISA I. (_CPU_Context_Initialize): Honor ISR level in task initialization. (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
2000-11-302000-11-30 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-2/+8
* cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to correct name of _CPU_Context_switch_restore. Added dummy version of exc_utlb_code() so applications would link.
2000-10-242000-10-24 Alan Cudmore <alanc@linuxstart.com> andJoel Sherrill1-94/+502
Joel Sherrill <joel@OARcorp.com> * This is a major reworking of the mips64orion port to use gcc predefines as much as possible and a big push to multilib the mips port. The mips64orion port was copied/renamed to mips to be more like other GNU tools. Alan did most of the technical work of determining how to map old macro names used by the mips64orion port to standard compiler macro definitions. Joel did the merge with CVS magic to keep individual file history and did the BSP modifications. Details follow: * Makefile.am: idtmon.h in mips64orion port not present. * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added. * cpu.c: Comments added. * cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added. First attempt at exception/interrupt processing for ISA level 1 and minus any use of IDT/MON added. * idtcpu.h: Conditionals changed to use gcc predefines. * iregdef.h: Ditto. * cpu_asm.h: No real change. Merger required commit. * rtems/Makefile.am: Ditto. * rtems/score/Makefile.am: Ditto. * rtems/score/cpu.h: Change MIPS64ORION to MIPS. * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
2000-07-11Removed no cpu references.Joel Sherrill1-1/+1
1999-11-17Updated copyright notice.Joel Sherrill1-2/+1
1999-05-18Patch from Daniel Kelley <dank@icube.com>:Joel Sherrill1-4/+4
I found a small buglet in the mips64orion _CPU_ISR_Set_level; the original was wiping out the level argument, and then comparing the current interrupt level with some random value of v0. See patch below.
1998-02-17updated copyright to 1998Joel Sherrill1-1/+1
1997-10-08Fixed typo in the pointer to the license terms.Joel Sherrill1-2/+2
1997-04-22headers updated to reflect new style copyright notice as partJoel Sherrill1-5/+5
of switching to the modified GNU GPL.
1996-09-11added $Id$ to file headersJoel Sherrill1-1/+1
cpu.h: added prototype for _CPU_ISR_Get_level()
1996-09-06new file for MIPS port by Craig Lebakken (lebakken@minn.net) andJoel Sherrill1-0/+972
Derrick Ostertag (ostertag@transition.com).
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