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* 2001-04-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-04-032-57/+1
| | | | | | | * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. * rtems/score/c4xtypes.h: Removed. * rtems/score/types.h: New file via CVS magic. * Makefile.am, rtems/score/cpu.h: Account for name change.
* 2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2002-01-302-35/+0
| | | | | | | * rtems/Makefile.am: Removed. * rtems/score/Makefile.am: Removed. * configure.ac: Reflect changes above. * Makefile.am: Reflect changes above.
* 2001-11-28 Joel Sherrill <joel@OARcorp.com>,Joel Sherrill2001-11-281-0/+7
| | | | | | | This was tracked as PR91. * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which is used to specify if the port uses the standard macro for this (FALSE). A TRUE setting indicates the port provides its own implementation.
* 2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-09-271-1/+1
| | | | | * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. * Makefile.am: Use 'PREINSTALL_FILES ='.
* 2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-02-051-3/+3
| | | | | * Makefile.am, rtems/score/Makefile.am: Apply include_*HEADERS instead of H_FILES.
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-031-0/+6
| | | | * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* 2000-10-18 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-10-181-5/+8
| | | | | * rtems/score/c4x.h: Modified to properly multilib. This required using only macros predefined by gcc.
* 2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-09-052-7/+6
| | | | | | * Makefile.am: Include compile.am, formatting. * rtems/Makefile.am: formatting. * rtems/score/Makefile.am: formatting.
* Port of RTEMS to the Texas Instruments C3x/C4x DSP families includingJoel Sherrill2000-07-262-0/+4
| | | | | | | | | | | a BSP (c4xsim) supporting the simulator included with gdb. This port was done by Joel Sherrill and Jennifer Averett of OAR Corporation. Also included with this port is a space/time optimization to eliminate FP context switch management on CPUs without hardware or software FP. An issue with this port was that sizeof(unsigned32) = sizeof(unsigned8) on this CPU. This required addressing alignment checks and assumptions as well as fixing code that assumed sizeof(unsigned32) == 4.
* BSP now compiles and links with CAVSL board information. This includesJoel Sherrill2000-02-291-3/+3
| | | | | | | | | | linkcmds updated, simio references removed, and switch to libchip for serial ports from simio. Added a MEMORY_MAP file to capture information about the various addresses on this board. In addition, many of the beta patches are now included.
* New port of RTEMS to TI C3x and C4x.Joel Sherrill2000-02-227-0/+1836
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