| Commit message (Collapse) | Author | Files | Lines |
|---|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Make sure that we do not use the stack for this function.
Update #4982.
|
|
Update #4982.
|
|
Do not clear SYSESR and let the application handle the reset source.
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Do not set pins to the default function before the actual setting is
applied. If a pin setting needs to be done in a certain order, then
this should be done explicitly through multiple calls to
tms570_bsp_pinmmr_config().
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Bit 1 of the PACT is reserved (writes have no effect).
Update #4982.
|
|
Update #4982.
|
|
Remove obsolete tms570ls3137_hdk_with_loader BSP variant. With the new
memory origin/size build options this variant is no longer required.
Update #4982.
|
|
Reserve the space in a section. This makes it possible to use a common
memory region definition.
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Rename tms570_initialize_and_clear() in
tms570_pom_initialize_and_clear().
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Change license to BSD-2-Clause according to file history and contributor
agreements. Add Doxygen file comments.
Update #3053.
Update #3707.
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
Update #4982.
|
|
This cleans up outputUsesInterrupts usage with rtems_termios_device_mode
enum values. The outputUsesInterrupts member was typed as an int, named
as if it were a boolean value, and used as if it were a
rtems_termios_device_mode enum. In this patch, values assigned to
outputUsesInterrupts have been converted to the corresponding
rtems_termios_device_mode enum value, conversions from
deviceOutputUsesInterrupts have been made explicit, and uses of
rtems_termios_device_mode enum values with deviceOutputUsesInterrupts
have been converted to booleans.
|
|
When the CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS definition was added
to AArch64 cache management, it obsoleted the *_1_data/instruction_line
functions. These have been removed since they are no longer referenced.
The AArch64_instruction_cache_inner_shareable_invalidate_all function is
only used when RTEMS_SMP is defined, so only define it in that
circumstance.
|
|
|
|
Let the BSP define TM27_INTERRUPT_VECTOR_DEFAULT to more efficiently and
reliably get the TM27 default interrupt vector.
Update #3716.
|
|
Expose functions to directly manipulate the bad block table (BBT). These
functions are necessary to correct possible BBT corruption caused by
bugs in the BBT management layer.
|
|
The XNandPsu_EraseBlock function takes a target device and a block
offset for erasure. Ensure the block offset is within the size of the
target device.
|
|
When marking the trailing blocks on a device as reserved for Bad Block
Table usage, ensure that the correct blocks are marked. This resolves an
off-by-one error that was marking one block too low and leaving the last
block in the device unmarked.
|
|
When writing out the Bad Block Table, write it to the targeted device
and ensure the block is appropriately mapped to the targeted device.
|
|
Mark the BBT descriptor as invalid before scanning to ensure that
missing BBTs are detected and written correctly if necessary.
|
|
The Bad Block Table is a per-device catalog of the dispositions of each
block in the device. Only read enough data to determine the dispositions
of blocks for the device being read.
|
|
The xnandpsu driver includes functionality to map back and forth between
the flash-based BBT and the memory-based BBT with the values in each
being a bitwise inversion of each other. This resolves several bugs in
this process and simplifies the inversion from operating on the block
representation to operating on the entire BBT entry (4 blocks, 2 bits
per block, one byte total).
Bugs resolved in XNandPsu_ConvertBbt():
* The calculation of memory BBT entry offset was off by a factor of 4
* The entry offset into the flash BBT has been removed since each flash
BBT directly describes the flash space it is contained within and has
no reference to other devices in the chip
Bugs resolved in XNandPsu_WriteBbt():
* The BBT length calculated was reduced to NumTargetBlocks from
NumBlocks since only the relevant portion of the in-memory BBT should
be written to the flash-based BBT space
* An offset was applied to values retrieved from the in-memory BBT so
that only the relevant portion was converted and written to the
flash-based BBT
|
|
The XNandPsu_IsBlockBad() function is insufficient for JFFS2 to
determine whether a block is usable since the function does not report
reserved blocks. JFFS2 is also unable to use the last 4 blocks of each
target attached to the NAND controller since they are reserved for the
Bad Block Table (BBT), but not necessarily marked as such.
|
|
Hi all, this is my first email patch submission and my first contribution to RTEMS, so please give any
feedback you have!
This patch enables interrupt driven data reception on USART ports on
STM32F4 series chips. This feature is gated behind the config flag
BSP_CONSOLE_USE_INTERRUPTS. If this flag is not set to True, the older
polling implementation will be used. I tested this feature on STM32F401CE
(blackpill) and STM32 Nucleo F411RE boards, with both capable of keeping
up with a 115200 baud continous data stream. With the older polling
implementation, both would drop bytes at 9600 baud. In addition, I
updated the implementation of usart_set_attributes to support changing
the baud rate of the USART port based on the input speed.
|
|
|
|
Place the vector table in the start section so that the overlay can be
avoided if we execute from internal flash. The problem is that when the
POM is enabled, the ECC cannot be enabled for the internal flash.
|
|
|
