summaryrefslogtreecommitdiffstats
path: root/bsps (unfollow)
Commit message (Expand)AuthorFilesLines
2023-01-12riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORTSebastian Huber6-12/+30
2023-01-04bsps/xil: Use the LP64 header for ILP32Kinsey Moore1-10/+25
2023-01-04bsps: Move ZynqMP-specific info into the BSPKinsey Moore3-117/+2
2023-01-03bsp/qoriq: Add qoriq_mmu_adjust_and_write_to_tlb1()Sebastian Huber3-7/+38
2023-01-03bsp/qoriq: Add qoriq_mmu_find_free_tlb1_entry()Sebastian Huber2-1/+27
2023-01-03bsp/qoriq: Support message signaled interruptsSebastian Huber2-17/+244
2023-01-03bsp/qoriq: Clear shared message signaled interruptsSebastian Huber1-0/+5
2023-01-03bsp/qoriq: Use only pic_is_ipi()Sebastian Huber1-11/+6
2022-12-23bsps: Import Xilinx NAND driverKinsey Moore10-0/+5622
2022-12-23bsps: Import Xilinx support codeKinsey Moore30-0/+5366
2022-12-23RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORTHesham Almatary6-26/+18
2022-12-15bsp/atsam: Allow to use custom SDRAMChristian Mauderer1-0/+7
2022-12-15bsps/atsam: Add NULL pointer protectionChristian Mauderer5-2/+28
2022-12-15bsps/atsam: Fix unidirectional SPI transfersChristian Mauderer1-57/+131
2022-12-07bsps/zynqmp: Fix and update device treesKinsey Moore4-115/+137
2022-12-02config: Add CONFIGURE_RECORD_INTERRUPTS_ENABLEDSebastian Huber1-0/+97
2022-12-02bsps/irq: Add bsp_interrupt_get_dispatch_table_slot()Sebastian Huber4-8/+26
2022-12-02bsps/irq: Rename handler in dispatch tableSebastian Huber6-59/+57
2022-11-29bsps/microblaze: Fix console interrupt build errorsAlex White3-1/+21
2022-11-23bsps/riscv: Simplify PLIC supportSebastian Huber1-28/+30
2022-11-23bsps/riscv: Fix PLIC enable register countSebastian Huber1-3/+5
2022-11-23bsps/riscv: Add riscv_plic_cpu_0_init()Sebastian Huber1-13/+23
2022-11-23bsps/riscv: Fix bsp_fdt_map_intr()Sebastian Huber1-1/+1
2022-11-22aarch64/versal: Add UART interrupt supportChris Johns4-39/+324
2022-11-22rtems/versal: Updated mmu to include mapping for SDHCI devices on versalAaron Nyholm1-1/+5
2022-11-18bsps/zynqmp: Use direct fdt_* callsKinsey Moore1-22/+10
2022-11-17aarch64/mmu: Prevent block descriptors at level -1Kinsey Moore1-10/+13
2022-11-14bsps/riscv: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman5-12/+90
2022-11-14bsps/sparc: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman40-132/+894
2022-11-14bsps/shared/grlib: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman67-199/+1453
2022-11-14bsps/include/grlib: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman59-168/+1319
2022-11-14bsps/include/libchip: Remove legacy networking header fileDaniel Cederman1-152/+0
2022-11-11bsps/riscv: Fix software interrupt dispatchingSebastian Huber2-2/+33
2022-11-11bsps/noel: Fix interrupt supportSebastian Huber1-0/+2
2022-11-10bsps/riscv: Fix PLIC enable register countSebastian Huber1-2/+2
2022-11-10bsps/riscv: Skip init on not configured processorsSebastian Huber1-0/+11
2022-11-10bsps/riscv: Simplify riscv_plic_init()Sebastian Huber1-30/+39
2022-11-10bsps/riscv: Simplify riscv_clint_init()Sebastian Huber1-14/+25
2022-11-10bsps/riscv: Add tm27 supportSebastian Huber1-1/+136
2022-11-10bsps/riscv: Always dispatch software interruptsSebastian Huber1-3/+2
2022-11-10bsps/riscv: bsp_interrupt_get/set_affinity()Sebastian Huber2-14/+7
2022-11-10bsps/riscv: bsp_interrupt_raise_on()Sebastian Huber1-4/+20
2022-11-10bsps/riscv: bsp_interrupt_is_pending()Sebastian Huber1-2/+25
2022-11-10bsps/riscv: bsp_interrupt_get_attributes()Sebastian Huber1-0/+15
2022-11-10bsps/riscv: Improve bsp_interrupt_vector_disable()Sebastian Huber1-0/+8
2022-11-10bsps/riscv: Improve bsp_interrupt_vector_enable()Sebastian Huber1-0/+8
2022-11-10bsps/riscv: bsp_interrupt_vector_is_enabled()Sebastian Huber1-2/+47
2022-11-10bsps/riscv: bsp_interrupt_is_valid_vector()Sebastian Huber2-1/+18
2022-11-09config: Place init task storage area in .rtemsstackSebastian Huber2-12/+12
2022-11-09bsps/aarch64: Ensure FPU trap state is consistentKinsey Moore1-0/+6
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-28 15:18:08 +0000