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The LEON3_Boot_Cpu global object is only used by start.S. Move the definition
of this object to start.S and use a local symbol .Lbootcpuindex for it.
Use a compare-and-swap instruction to assign the boot CPU. This allows a
concurrent initialization.
Close #4845.
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This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
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Move _ISR_Handler() to a separate file since it is now only used if a handler
is installed by _CPU_ISR_install_raw_handler().
Statically initialize the traps for external interrupts to use the new
_SPARC_Interrupt_trap() which directly dispatches the interrupt handlers
installed by rtems_interrupt_handler_install() via the BSP-provided
_SPARC_Interrupt_dispatch().
Since the trap table is now fully statically initialized, there is no longer a
dependency on the Cache Manager in the default configuration.
Update #4458.
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Statically initialize the trap table in start.S to jump to _SPARC_Bad_trap()
for all unexpected traps. This enables a proper RTEMS fatal error handling
right from the start. Do not rely on the stack and register settings which
caused an unexpected trap. Use the ISR stack of the processor to do the fatal
error handling. Save the full context which caused the trap. Fatal error
handler may use it for error logging.
Unify the _CPU_Exception_frame_print() implementations and move it to cpukit.
Update #4459.
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This makes it easier to review start.o and set break points to trap table
entries. This change was checked by inspecting the trap table in start.o with
objdump.
Update #4458.
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Directly initialize the memory in the start sequence defined by start.S
instead of using a system initialization handler. This avoids using the
global variable rdb_start which used a memory location which was shared
with _ERC32_MEC_Timer_Control_Mirror. This change makes it possible to
use _Memory_Allocate() even before the system initialization is started.
Change license to BSD-2-Clause according to file history and
re-licensing agreement.
Update #3053.
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Initialize the stacks for all processors in one place. Do not rely on
Per_CPU_Control::interrupt_stack_high and directly use the statically
allocated interrupt stack area.
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Initialize the stacks in start.S in one place and identical to
_CPU_Context_Initialize().
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Remove the support to load the data section and rely on the boot loader. The
code is an artifact from the old erc32 days, when we would boot and execute
from ROM and the .data had to be copied over to RAM. With leon1/2/3, this is
not used anymore as a boot loader is made from the RAM image using a custom
tool (mkprom).
In SMP configurations, this support was also broken since LEON3_Boot_Cpu
(in the data section due to the -1 initialization value) was used quite
early in the start sequence.
If the data copy is really necessary, then an application can still add this
step as a very early system initialization step, since boot_card() and the
system initialization loop does not use initialized read-write data (only
read-only and BSS data). However, the SMP startup would still not work in this
case. A boot loader is a better place to load the sections.
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Rename
* _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin,
* _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and
* _Configuration_Interrupt_stack_size in _ISR_Stack_size.
Move definitions to <rtems/score/isr.h>. The new names are considerable
shorter and in the right namespace.
Update #3459.
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Fix typo in start.S introduced by
4678d1a8b0e74a12809122ef071324c99e78d7ff.
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Pass current processor control as first parameter in
bsp_start_on_secondary_processor() and qoriq_start_thread() to make
dependency more explicit.
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Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).
This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.
This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.
Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).
The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.
The initialization stack can reuse the interrupt stack, since
* interrupts are disabled during the sequential system initialization,
and
* the boot_card() function does not return.
This stack resuse saves memory.
Changes per architecture:
arm:
* Mostly replace the linker symbol based configuration of stacks with
the standard <rtems/confdefs.h> configuration via
CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND
mode stack is still defined via linker symbols. These modes are
rarely used in applications and the default values provided by the
BSP should be sufficient in most cases.
* Remove the bsp_processor_count linker symbol hack used for the SMP
support. This is possible since the interrupt stack area is now
allocated by the linker and not allocated from the heap. This makes
some configure.ac stuff obsolete. Remove the now superfluous BSP
variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.
bfin:
* Remove unused magic linker command file allocation of initialization
stack. Maybe a previous linker command file copy and paste problem?
In the start.S the initialization stack is set to a hard coded value.
lm32, m32c, mips, nios2, riscv, sh, v850:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
m68k:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
powerpc:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
* Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
stack on BSPs using the shared linkcmds.base (replacement for
REGION_RWEXTRA).
sparc:
* Remove the hard coded initialization stack. Use the interrupt stack
for the initialization stack on the boot processor. This saves
16KiB of RAM.
Update #3459.
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This patch is a part of the BSP source reorganization.
Update #3285.
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The SPARC ABI is a bit special with respect to the floating point context.
The complete floating point context is volatile. Thus, from an ABI point
of view nothing needs to be saved and restored during a context switch.
Instead the floating point context must be saved and restored during
interrupt processing. Historically, the deferred floating point switch was
used for SPARC and the complete floating point context is saved and
restored during a context switch to the new floating point unit owner.
This is a bit dangerous since post-switch actions (e.g. signal handlers)
and context switch extensions may silently corrupt the floating point
context.
The floating point unit is disabled for interrupt handlers. Thus, in case
an interrupt handler uses the floating point unit then this will result in a
trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT).
In uniprocessor configurations, a lazy floating point context switch is
used. In case an active floating point thread is interrupted (PSR[EF] == 1)
and a thread dispatch is carried out, then this thread is registered as the
floating point owner. When a floating point owner is present during a
context switch, the floating point unit is disabled for the heir thread
(PSR[EF] == 0). The floating point disabled trap checks that the use of the
floating point unit is allowed and saves/restores the floating point context
on demand.
Update #3077.
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The SYM define concatenates the input with the compiler set
__USER_LABEL_PREFIX__ define. This define appears to be '_' in GCC but
empty in Clang. Therefore when compiling with Clang/LLVM 'SYM(start)'
and 'start' defines the same symbol, and the compiler complains that the
symbol is defined twice.
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- All references of %0 changed to %g0
- 'call label,0' changed to 'call label'. According to the sparc
specification call does not take any registers
- '.seg "text"' changed to '.section ".text"'
- the synonym stub is replaced with stb
- the synonym stuh is replaced with sth
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closes #2810.
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Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the
PSR[EF] state of the interrupted context via new system call
syscall_irqdis_fp in case floating-point support is enabled.
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Rename SPARC-specific CPU_Minimum_stack_frame to
SPARC_Minimum_stack_frame. Rename SPARC-specific
CPU_MINIMUM_STACK_FRAME_SIZE to SPARC_MINIMUM_STACK_FRAME_SIZE.
Update #2809.
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The text and data sections may have different alignment requirements.
Support a data section alignment greater than 16.
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The window underflow trap handler used %i5 which destroyed the %o5 of
the calling context. Bug introduced by
0d3b5d47429effb350448d9e9123a67db722109f.
Go back to the pre 0d3b5d47429effb350448d9e9123a67db722109f behaviour
and use the two unused instructions in the trap vector to optimize a
bit.
Update #2651.
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* Coding style cleanups.
* Use OS reserved trap 0x89 for IRQ Disable
* Use OS reserved trap 0x8A for IRQ Enable
* Add to SPARC CPU supplement documentation
This will result in faster Disable/Enable code since the
system trap handler does not need to decode which function
the user wants. Besides the IRQ disable/enabled can now
be inline which avoids the caller to take into account that
o0-o7+g1-g4 registers are destroyed by trap handler.
It was also possible to reduce the interrupt trap handler by
five instructions due to this.
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Save five instructions on underflow handling.
By using an optimized trap entry we can move instructions from
the window underflow function into the trap entry vector. By
setting WIM=0 and using RESTORE it is possible to move the
new WIM register content from the trapped window into the
to-be-restored register window. It is then possible to avoid
the WIM write delay.
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I see no need for waiting the 3 instruction delay for wim to be
written in this case, since the STD after does not depend on WIM
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Now that a SPARC fatal handler is defined, we no longer
need the BSP specific reset routine.
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Instead of calling the system call TA instruction directly it
is better paractise to isolate the trap implementation to the
system call functions.
BSP_fatal_exit() is added.
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The last optimization missed was incorrect in regards to
PSR write instruction delay must be 3 instructions.
New optimizations:
* align to 32-byte cache line.
* rearrange code into three "blocks" of 4 instructions that
is executed by syscall 2 and 3. This is to optimize for
16/32 byte cache lines.
* use delay-slot instruction in trap table to reduce by one
instruction.
* use the fact that "wr %PSR" implements XOR to reduce by
one instruction.
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Use __bss_start available via %g2 to clear the BSS section. The usage
of _edata resulted in a copy of [_edata, __bss_start) from ROM to RAM
and then a clear to zero of this area.
Clear now only [__bss_start, _end).
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Use the register %g4 for the data content since it must be an even
numbered register due to the std/ldd. Use the register %g2 for the BSS
start address, so that it can be later re-used for the BSS zero loop.
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Use a standard function for startup on secondary processors.
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Use register g6 for the per-CPU control of the current processor. The
register g6 is reserved for the operating system by the SPARC ABI. On
Linux register g6 is used for a similar purpose with the same method
since 1996.
The register g6 must be initialized during system startup and then must
remain unchanged.
Since the per-CPU control is used in all critical sections of the
operating system, this is a performance optimization for the operating
system core procedures. An additional benefit is that the low-level
context switch and interrupt processing code is now identical on non-SMP
and SMP configurations.
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Add _LEON3_Get_current_processor().
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Avoid usage of the same stack area by multiple secondary processors at
the same time.
Avoid magic delay loops.
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Add doxygen to the header files in sparc/shared/include directory.
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There is no point having interrupts enabled before reaching
boot_card() that disables interrupt. We better have it off
all the time.
It is required to turn off interrupt on secondary CPUs in an
SMP system.
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This is declared in <bsp/bootcard.h> and is the usual function to reset
a board.
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Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
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Jennifer Averett <jennifer.averett@OARcorp.com>
PR 1801/bsps
* shared/start.S: Add SMP support to LEON3 BSP.
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* shared/start.S: Fix comment.
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* shared/start.S: Checked and OK.
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