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* bsps: Mark argument as unusedSebastian Huber2023-04-051-0/+1
| | | | Update #4862.
* bsps/xqspipsu: Add support for reading ECCKinsey Moore2023-03-221-0/+223
| | | | | This adds a helper function to read the ECC status for an ECC unit in SPI-attached NOR memory.
* doxygen: Add Doxygen files to a groupSebastian Huber2023-02-161-0/+8
| | | | Update #3707.
* bsps/nand: Update Xilinx NAND driverKinsey Moore2023-01-304-17/+23
| | | | | This resovles gcc warnings by updating to the latest Xilinx NAND controller driver.
* grlib: Fix snprintf() overflow warnings from gcc 12Joel Sherrill2023-01-3013-14/+14
| | | | Updates #4662.
* bsps: Add Xilinx GQSPI flash helperAlex White2023-01-271-0/+2005
| | | | | | This adds helper functions for working with NOR flash connected to the Xilinx GQSPI controller. The helper functions are based on Xilinx's QSPIPSU flash interrupt example.
* bsps: Import Xilinx GQSPI driverAlex White2023-01-275-0/+2659
| | | | | | | | This adds Xilinx's driver for the Xilinx GQSPI controller embedded in the ZynqMP SoC. Within that device alone, it is possible to access this peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/dev/spi/VERSION.
* intr: Add Interrupt Manager implementation groupSebastian Huber2023-01-2416-16/+16
| | | | | | | The shared BSP interrupt controller support code actually implements parts of the Interrupt Manager. Update #3706.
* clockdrv: Add clock driver implementation groupSebastian Huber2023-01-241-10/+13
| | | | | | Use standard wording in Clock Driver related files. Update #3706.
* bsps: Move ZynqMP-specific info into the BSPKinsey Moore2023-01-042-117/+0
| | | | | | The address of the nandpsu peripheral is specific to the ZynqMP SoC and not relevant to other devices that might have one or more instances of this peripheral.
* bsps: Import Xilinx NAND driverKinsey Moore2022-12-236-0/+4062
| | | | | | | | | | This adds Xilinx's driver for the Xilinx NAND controller embedded in the ZynqMP SoC. Within that device alone, it is possible to access this peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added to the hardware ZynqMP BSPs since QEMU does not support emulation of this peripheral. This driver supports polled operation only. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/dev/nand/VERSION.
* bsps: Import Xilinx support codeKinsey Moore2022-12-234-0/+948
| | | | | | | | | This support code is necessary for many Xilinx-provided bare metal device drivers supported on ARM, AArch64, and MicroBlaze platforms. Support for all of these architectures is kept under bsps/include due to multiple architecture variants being supported which requires complex logic in the build system. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/xil/VERSION.
* config: Add CONFIGURE_RECORD_INTERRUPTS_ENABLEDSebastian Huber2022-12-021-0/+97
| | | | | | | | This enables the tracing of interrupt entry/exit events through an application configuration option. The interrupt processing can be viewed with Trace Compass using rtems-record-lttng from the RTEMS Tools. Update #4769.
* bsps/irq: Add bsp_interrupt_get_dispatch_table_slot()Sebastian Huber2022-12-023-8/+15
| | | | Update #4769.
* bsps/irq: Rename handler in dispatch tableSebastian Huber2022-12-023-21/+21
| | | | | | | The name handler table was a bit misleading after the last rework. Rename it to distach table. Update the documentation accordingly. Update #4769.
* bsps/shared/grlib: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman2022-11-1467-199/+1453
| | | | | | | | | This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
* bsps: Add Cache Manager implementation groupSebastian Huber2022-10-241-4/+39
| | | | Update #3707.
* bsps: Fix format specifierSebastian Huber2022-09-231-1/+1
| | | | Close #4722.
* bsps/shared/: Use device tree blobPadmarao Begari2022-09-201-0/+8
| | | | | | If the bsp is integrated and supported a device tree blob(dtb) then use dtb instead of using it from the U-Boot (BSP_START_COPY_FDT_FROM_U_BOOT=False).
* bsps/shared/*: Change license to BSD-2Joel Sherrill2022-06-1574-222/+1628
| | | | Updates #3053.
* bsps: Add gicv3_get_attributes()Sebastian Huber2022-04-061-26/+1
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* bsps: Add gicv3_sgi_ppi_get_priority()Sebastian Huber2022-04-061-3/+4
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* bsps: Add gicv3_sgi_ppi_set_priority()Sebastian Huber2022-04-061-3/+5
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* bsps: Move gicv3_init_cpu_interface()Sebastian Huber2022-04-061-30/+2
| | | | Make the processor index a parameter.
* bsps: Move gicv3_init_dist()Sebastian Huber2022-04-061-39/+1
| | | | Make the distributor register block a parameter.
* bsps: Add gicv3_sgi_ppi_disable()Sebastian Huber2022-04-061-4/+1
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* bsps: Add gicv3_sgi_ppi_enable()Sebastian Huber2022-04-061-9/+1
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* bsps: Add gicv3_sgi_ppi_is_enabled()Sebastian Huber2022-04-061-4/+1
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* bsps: Add gicv3_ppi_clear_pending()Sebastian Huber2022-04-061-4/+1
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* bsps: Add gicv3_ppi_set_pending()Sebastian Huber2022-04-061-4/+1
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* bsps: Add gicv3_trigger_sgi()Sebastian Huber2022-04-061-14/+1
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* bsps: Add gicv3_sgi_ppi_is_pending()Sebastian Huber2022-04-061-4/+1
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* bsps: Add <dev/irq/arm-gicv3.h>Sebastian Huber2022-04-061-121/+1
| | | | | | | | Separate the Interrupt Manager implementation from the generic Arm GICv3 support. Move parts of the Arm GICv3 support into a new header file. This helps to support systems with a clustered structure in which multiple GICv3 instances are present. For example, two clusters of two Cortex-R52 cores where each cluster has a dedicated GICv3 instance.
* bsps/irq: Improve affinity set handlingSebastian Huber2022-03-161-1/+7
| | | | | | | | Restrict the affinity set to the set of online processors. Make sure the affinity set for an interrupt vector contains at least one online processor. Update #3269.
* bsps/irq: Fix formattingSebastian Huber2022-03-161-3/+3
| | | | Update #3269.
* bsps/shared: Manual file header clean upChristian Mauderer2022-03-107-125/+87
| | | | Updates #4625.
* bsps/shared/: Scripted embedded brains header file clean upJoel Sherrill2022-03-1025-122/+14
| | | | Updates #4625.
* bsp/leon3: Include missing header fileSebastian Huber2022-03-081-0/+1
| | | | | The <leon.h> include was removed from <bsp.h> in commit 1577a48369fae5e024baa2119b26d25de0f43946.
* bsps: Avoid use of memcpy() in bsp_fdt_copy()Sebastian Huber2022-01-191-1/+1
| | | | | The memcpy() function may be not loaded at the time bsp_fdt_copy() is called.
* bsps: Default to CPU counter benchmark timerSebastian Huber2022-01-151-30/+0
| | | | | | Most BSPs which used the stubbed benachmark timer provide a CPU counter. All BSPs provide at least a stub CPU counter. Simply use the benchmark timer implementation using the CPU counter.
* aarch64: always boot into EL1NSGedare Bloom2022-01-121-12/+3
| | | | | | | | | | | Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
* arm/gicv3: refactor DIST initialization to helperGedare Bloom2022-01-121-31/+29
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* Fix device tree blob alignmentSebastian Huber2022-01-111-4/+4
| | | | A device tree blob must be aligned on an 8-byte boundary.
* libc: Optimize malloc() initializationSebastian Huber2021-11-302-0/+98
| | | | | | | | | | | | | | | | The BSPs provide memory for the separate C Program Heap initialization via _Memory_Get(). Most BSPs provide exactly one memory area. Only two BSPs provide more than one memory area (arm/altera-cyclone-v and bsps/powerpc/mpc55xxevb). Only if more than one memory area is provided, there is a need to use _Heap_Extend(). Provide two implementations to initialize the separate C Program Heap and let the BSP select one of the implementations based on the number of provided memory areas. This gets rid of a dependency on _Heap_Extend(). It also avoids dead code sections for most BSPs. Change licence to BSD-2-Clause according to file history. Update #3053.
* score: Optimize Workspace Handler initializationSebastian Huber2021-11-302-0/+92
| | | | | | | | | | | | The BSPs provide memory for the workspace initialization via _Memory_Get(). Most BSPs provide exactly one memory area. Only two BSPs provide more than one memory area (arm/altera-cyclone-v and bsps/powerpc/mpc55xxevb). Only if more than one memory area is provided, there is a need to use _Heap_Extend(). Provide two implementations to initialize the workspace handler and let the BSP select one of the implementations based on the number of provided memory areas. This gets rid of a dependency on _Heap_Extend(). It also avoids dead code sections for most BSPs.
* bsps/gicv2: Allow BSPs to define IRQ attributesKinsey Moore2021-09-213-34/+180
| | | | | | | ARM's GICv2 is configurable and its attributes vary between implementations including omission of specific interrupts. This allows BSPs to accomodate those varying implementations with customized attribute sets.
* bsps/shared: Add PSCI SMP startup supportKinsey Moore2021-09-211-0/+92
| | | | | | | | This adds the SMP function that supports spinup of additional CPU cores using the ARM standard PSCI inteface. This interface is provided by QEMU as well as ARM Trusted Firmware running in monitor mode (EL3) on ARMv7 and AArch64 CPUs. This supports activation va SMC or HVC instructions depending on BSP configuration.
* build: Remove old build systemSebastian Huber2021-09-214-151/+0
| | | | | Close #3250. Close #4081.
* arm/xilinx: Fix zynq-uart interrupt receiveChris Johns2021-09-162-57/+66
| | | | | | | | - Trigger on a single character entering the RX FIFO - Disable the RX timeout - Send up to a FIFO full of data
* bsps/zynq: Moved general i2c files to shared directoriesStephen Clark2021-09-091-0/+482
| | | | | Certain files related to the Zynq BSP's I2C driver are useable by the ZynqMP BSP as well. Moved these files to shared directory in anticipation of I2C support for ZynqMP.
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