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* bsps: Import Xilinx GQSPI driverAlex White2023-01-275-0/+2659
| | | | | | | | This adds Xilinx's driver for the Xilinx GQSPI controller embedded in the ZynqMP SoC. Within that device alone, it is possible to access this peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/dev/spi/VERSION.
* clockdrv: Add clock driver implementation groupSebastian Huber2023-01-241-10/+13
| | | | | | Use standard wording in Clock Driver related files. Update #3706.
* bsps: Move ZynqMP-specific info into the BSPKinsey Moore2023-01-042-117/+0
| | | | | | The address of the nandpsu peripheral is specific to the ZynqMP SoC and not relevant to other devices that might have one or more instances of this peripheral.
* bsps: Import Xilinx NAND driverKinsey Moore2022-12-236-0/+4062
| | | | | | | | | | This adds Xilinx's driver for the Xilinx NAND controller embedded in the ZynqMP SoC. Within that device alone, it is possible to access this peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added to the hardware ZynqMP BSPs since QEMU does not support emulation of this peripheral. This driver supports polled operation only. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/dev/nand/VERSION.
* bsps/shared/*: Change license to BSD-2Joel Sherrill2022-06-1548-144/+1056
| | | | Updates #3053.
* bsps: Add gicv3_get_attributes()Sebastian Huber2022-04-061-26/+1
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* bsps: Add gicv3_sgi_ppi_get_priority()Sebastian Huber2022-04-061-3/+4
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* bsps: Add gicv3_sgi_ppi_set_priority()Sebastian Huber2022-04-061-3/+5
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* bsps: Move gicv3_init_cpu_interface()Sebastian Huber2022-04-061-30/+2
| | | | Make the processor index a parameter.
* bsps: Move gicv3_init_dist()Sebastian Huber2022-04-061-39/+1
| | | | Make the distributor register block a parameter.
* bsps: Add gicv3_sgi_ppi_disable()Sebastian Huber2022-04-061-4/+1
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* bsps: Add gicv3_sgi_ppi_enable()Sebastian Huber2022-04-061-9/+1
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* bsps: Add gicv3_sgi_ppi_is_enabled()Sebastian Huber2022-04-061-4/+1
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* bsps: Add gicv3_ppi_clear_pending()Sebastian Huber2022-04-061-4/+1
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* bsps: Add gicv3_ppi_set_pending()Sebastian Huber2022-04-061-4/+1
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* bsps: Add gicv3_trigger_sgi()Sebastian Huber2022-04-061-14/+1
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* bsps: Add gicv3_sgi_ppi_is_pending()Sebastian Huber2022-04-061-4/+1
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* bsps: Add <dev/irq/arm-gicv3.h>Sebastian Huber2022-04-061-121/+1
| | | | | | | | Separate the Interrupt Manager implementation from the generic Arm GICv3 support. Move parts of the Arm GICv3 support into a new header file. This helps to support systems with a clustered structure in which multiple GICv3 instances are present. For example, two clusters of two Cortex-R52 cores where each cluster has a dedicated GICv3 instance.
* bsps/shared: Manual file header clean upChristian Mauderer2022-03-107-125/+87
| | | | Updates #4625.
* bsps/shared/: Scripted embedded brains header file clean upJoel Sherrill2022-03-1022-104/+14
| | | | Updates #4625.
* bsps: Default to CPU counter benchmark timerSebastian Huber2022-01-151-30/+0
| | | | | | Most BSPs which used the stubbed benachmark timer provide a CPU counter. All BSPs provide at least a stub CPU counter. Simply use the benchmark timer implementation using the CPU counter.
* aarch64: always boot into EL1NSGedare Bloom2022-01-121-12/+3
| | | | | | | | | | | Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
* arm/gicv3: refactor DIST initialization to helperGedare Bloom2022-01-121-31/+29
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* bsps/gicv2: Allow BSPs to define IRQ attributesKinsey Moore2021-09-213-34/+180
| | | | | | | ARM's GICv2 is configurable and its attributes vary between implementations including omission of specific interrupts. This allows BSPs to accomodate those varying implementations with customized attribute sets.
* arm/xilinx: Fix zynq-uart interrupt receiveChris Johns2021-09-162-57/+66
| | | | | | | | - Trigger on a single character entering the RX FIFO - Disable the RX timeout - Send up to a FIFO full of data
* bsps/zynq: Moved general i2c files to shared directoriesStephen Clark2021-09-091-0/+482
| | | | | Certain files related to the Zynq BSP's I2C driver are useable by the ZynqMP BSP as well. Moved these files to shared directory in anticipation of I2C support for ZynqMP.
* bsps/irq: bsp_interrupt_facility_initialize()Sebastian Huber2021-07-272-4/+2
| | | | | | Do not return a status code in bsp_interrupt_facility_initialize() since this leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG assertions in bsp_interrupt_facility_initialize() if necessary.
* bsps/irq: Implement new directives for GICv2/3Sebastian Huber2021-07-262-31/+185
| | | | Update #3269.
* bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber2021-07-262-2/+4
| | | | | | Return a status code for bsp_interrupt_set_affinity(). Update #3269.
* bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber2021-07-262-2/+4
| | | | | | Return a status code for bsp_interrupt_get_affinity(). Update #3269.
* bsps/irq: bsp_interrupt_vector_disable()Sebastian Huber2021-07-262-2/+5
| | | | | | Return a status code for bsp_interrupt_vector_disable(). Update #3269.
* bsps/irq: bsp_interrupt_vector_enable()Sebastian Huber2021-07-262-2/+5
| | | | | | Return a status code for bsp_interrupt_vector_enable(). Update #3269.
* bsps/irq: Add rtems_interrupt_is_pending()Sebastian Huber2021-07-262-0/+22
| | | | | | Add a default implementation which just returns RTEMS_UNSATISFIED. Update #3269.
* bsps/irq: Add rtems_interrupt_get_attributes()Sebastian Huber2021-07-262-0/+16
| | | | | | | Add a default implementation which clears the attributes to zero and just returns RTEMS_SUCCESSFUL for valid parameters. Update #3269.
* bsps/irq: Add rtems_interrupt_raise()Sebastian Huber2021-07-262-0/+46
| | | | | | | | | Add rtems_interrupt_raise_on() and rtems_interrupt_clear(). Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
* bsps/irq: Add rtems_interrupt_vector_is_enabled()Sebastian Huber2021-07-262-0/+22
| | | | | | | Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
* bsps: Fix GICv3 support for AArch32Sebastian Huber2021-06-301-3/+3
| | | | | | | | | | | The GICv3 support is shared between AArch32 and AArch64. For AArch32, the new AARCH64_IS_NONSECURE is never defined. Use ARM_MULTILIB_ARCH_V4 instead. This issue was introduced by 76c6caad52244ab9a14151620a80ff0f71035b6c. There is still a change in bsp_interrupt_vector_enable() for AArch32 compared to the version before 76c6caad52244ab9a14151620a80ff0f71035b6c.
* bsps/zynq-uart: Make post baud change kick globalKinsey Moore2021-06-292-0/+14
| | | | | | | | The existing fix for the ZynqMP UART hardware bug only caught the vast majority of instances where it could occur. To fully fix the data corruption, this fix must be applied after every baud rate change. This makes the logic reset and kick apply in any locations where the baud rate could be changed.
* bsps/aarch64: add non-secure mode and versal supportGedare Bloom2021-06-241-2/+21
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* bsps/aarch64: add mnemonic for ICC_IGRPEN1_EL3Gedare Bloom2021-06-241-0/+1
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* rtems: Constify rtems_task_wake_when()Sebastian Huber2021-05-121-1/+1
| | | | | | | | | | | | | | | | Add a parameter to _TOD_Validate() to disable the validation of the ticks member. There are two reasons for this change. Firstly, in rtems_task_wake_when() was a double check for time_buffer == NULL (one in rtems_task_wake_when() and one in _TOD_Validate()). Secondly, the ticks member is ignored by rtems_task_wake_when(). This was done with a write of zero to the ticks member and thus a modification of the user-provided structure. Now the structure is no longer modified. Using a mask parameter is quite efficient. You just have to load an immediate value and there are no additional branches in _TOD_Validate(). Close #4406.
* _TOD_Validate(): Fix incorrect return codeFrank Kühndel2021-05-121-1/+1
| | | | | | | | | | | | | | | This patch fixes bug #4403. Directives * rtems_timer_fire_when() * rtems_timer_server_fire_when() * rtems_task_wake_when() are documented to return RTEMS_INVALID_ADDRESS when their time-of-day argument is NULL. But actually they return RTEMS_INVALID_CLOCK. To fix the issue this patch changes _TOD_Validate() to return a status code instead of just true/false. Close #4403
* bsps/xilinx-zynqmp: Avoid constant UART reinitKinsey Moore2021-04-191-3/+6
| | | | | | Constantly reinitializing the Cadence UART on every character output causes data corruption/loss on some ZynqMP hardware. Only initialize the UART once for early output and give it a kick on startup.
* disp_hcms29xx.c: Unused value (CID #1399752)Ryan Long2021-04-081-1/+3
| | | | | | CID 1399752: Unused value in disp_hcms29xx_update_task(). Closes #4342
* bsps/xilinx_zynq: Add SPI driver for xilinx-axi-spiJan Sommer2021-03-301-0/+402
| | | | Updates #4321
* bsps/xilinx_zynq: Add SPI driver for cadence-spiJan Sommer2021-03-101-0/+444
| | | | Updates #4320
* bsps/shared: Allow setting baud rate for zynq uartJan Sommer2021-03-051-5/+16
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* bsps/shared: Adapt fsl-edma driver for imxrtChristian Mauderer2021-01-211-104/+245
| | | | | | | | | | Note: The changes have been done with portability in mind. The driver should (in theory) be able to replace the original one in the MPC BSPs too. For full compatibility an adaption layer and especially a test would be necessary. Because both are missing, don't integrate it into the MPC BSP now. Update #4180
* bsps/shared: Copy fsl-edma from mpc55xxChristian Mauderer2021-01-211-0/+329
| | | | | | This is a preparation for making the driver universal. Update #4180
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-232-0/+2
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
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