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2024-04-16bsps/arm: Improve GICv3 supportSebastian Huber1-5/+11
In addtion to 1023, the GICC_IAR register may return 1022 as a special value. Simply check for a valid interrupt vector for the dispatching. Check the GICC_IAR again after the dispatch to quickly process a next interrupt without having to go through the interrupt prologue and epiloge.
2024-04-16dev/irq: Improve Doxgyen group assignmentsSebastian Huber4-8/+21
Make the GIC interrupt controller support a subgroup of the generic interrupt controller support.
2024-04-16bsps/arm: Improve GICv2 supportSebastian Huber1-5/+20
In addtion to 1023, the GICC_IAR register may return 1022 as a special value. Simply check for a valid interrupt vector for the dispatching. Check the GICC_IAR again after the dispatch to quickly process a next interrupt without having to go through the interrupt prologue and epiloge.
2024-04-09bsps: Include <rtems/score/processormaskimpl.h>Sebastian Huber2-0/+2
This fixes commit b678a199e499b6c3f0b453393434aefaee180423 for SMP configurations.
2024-03-27bsps: Move declarations to <bsp/irq-generic.h>Sebastian Huber2-2/+4
Move declarations of bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() to <bsp/irq-generic.h>. Canonicalize the <bsp/irq.h> includes. Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if needed (usually RTEMS_SMP). Provide stub implementations for i386 to fix build errors.
2024-03-20dev/irq: Optional arm_gic_irq_processor_count()Sebastian Huber2-0/+4
Provide arm_gic_irq_processor_count() only in SMP configurations.
2023-05-26bsps: Improve Doxygen file commentsSebastian Huber1-0/+8
2023-05-20Update company nameSebastian Huber2-2/+2
The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
2022-06-15bsps/shared/*: Change license to BSD-2Joel Sherrill1-3/+22
Updates #3053.
2022-04-06bsps: Add gicv3_get_attributes()Sebastian Huber1-26/+1
2022-04-06bsps: Add gicv3_sgi_ppi_get_priority()Sebastian Huber1-3/+4
2022-04-06bsps: Add gicv3_sgi_ppi_set_priority()Sebastian Huber1-3/+5
2022-04-06bsps: Move gicv3_init_cpu_interface()Sebastian Huber1-30/+2
Make the processor index a parameter.
2022-04-06bsps: Move gicv3_init_dist()Sebastian Huber1-39/+1
Make the distributor register block a parameter.
2022-04-06bsps: Add gicv3_sgi_ppi_disable()Sebastian Huber1-4/+1
2022-04-06bsps: Add gicv3_sgi_ppi_enable()Sebastian Huber1-9/+1
2022-04-06bsps: Add gicv3_sgi_ppi_is_enabled()Sebastian Huber1-4/+1
2022-04-06bsps: Add gicv3_ppi_clear_pending()Sebastian Huber1-4/+1
2022-04-06bsps: Add gicv3_ppi_set_pending()Sebastian Huber1-4/+1
2022-04-06bsps: Add gicv3_trigger_sgi()Sebastian Huber1-14/+1
2022-04-06bsps: Add gicv3_sgi_ppi_is_pending()Sebastian Huber1-4/+1
2022-04-06bsps: Add <dev/irq/arm-gicv3.h>Sebastian Huber1-121/+1
Separate the Interrupt Manager implementation from the generic Arm GICv3 support. Move parts of the Arm GICv3 support into a new header file. This helps to support systems with a clustered structure in which multiple GICv3 instances are present. For example, two clusters of two Cortex-R52 cores where each cluster has a dedicated GICv3 instance.
2022-03-10bsps/shared/: Scripted embedded brains header file clean upJoel Sherrill2-12/+0
Updates #4625.
2022-01-12aarch64: always boot into EL1NSGedare Bloom1-12/+3
Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
2022-01-12arm/gicv3: refactor DIST initialization to helperGedare Bloom1-31/+29
2021-09-21bsps/gicv2: Allow BSPs to define IRQ attributesKinsey Moore3-34/+180
ARM's GICv2 is configurable and its attributes vary between implementations including omission of specific interrupts. This allows BSPs to accomodate those varying implementations with customized attribute sets.
2021-07-27bsps/irq: bsp_interrupt_facility_initialize()Sebastian Huber2-4/+2
Do not return a status code in bsp_interrupt_facility_initialize() since this leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG assertions in bsp_interrupt_facility_initialize() if necessary.
2021-07-26bsps/irq: Implement new directives for GICv2/3Sebastian Huber2-31/+185
Update #3269.
2021-07-26bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber2-2/+4
Return a status code for bsp_interrupt_set_affinity(). Update #3269.
2021-07-26bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber2-2/+4
Return a status code for bsp_interrupt_get_affinity(). Update #3269.
2021-07-26bsps/irq: bsp_interrupt_vector_disable()Sebastian Huber2-2/+5
Return a status code for bsp_interrupt_vector_disable(). Update #3269.
2021-07-26bsps/irq: bsp_interrupt_vector_enable()Sebastian Huber2-2/+5
Return a status code for bsp_interrupt_vector_enable(). Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_is_pending()Sebastian Huber2-0/+22
Add a default implementation which just returns RTEMS_UNSATISFIED. Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_get_attributes()Sebastian Huber2-0/+16
Add a default implementation which clears the attributes to zero and just returns RTEMS_SUCCESSFUL for valid parameters. Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_raise()Sebastian Huber2-0/+46
Add rtems_interrupt_raise_on() and rtems_interrupt_clear(). Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_vector_is_enabled()Sebastian Huber2-0/+22
Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
2021-06-30bsps: Fix GICv3 support for AArch32Sebastian Huber1-3/+3
The GICv3 support is shared between AArch32 and AArch64. For AArch32, the new AARCH64_IS_NONSECURE is never defined. Use ARM_MULTILIB_ARCH_V4 instead. This issue was introduced by 76c6caad52244ab9a14151620a80ff0f71035b6c. There is still a change in bsp_interrupt_vector_enable() for AArch32 compared to the version before 76c6caad52244ab9a14151620a80ff0f71035b6c.
2021-06-24bsps/aarch64: add non-secure mode and versal supportGedare Bloom1-2/+21
2021-06-24bsps/aarch64: add mnemonic for ICC_IGRPEN1_EL3Gedare Bloom1-0/+1
2020-12-23bsps: Use header file for GIC architecture supportSebastian Huber2-0/+2
This avoids a function call overhead in the interrupt dispatching. Update #4202.
2020-12-22bsps: Fix includesSebastian Huber1-0/+6
Update #4202.
2020-12-16bsps: Remove gicvx_interrupt_dispatch()Sebastian Huber2-2/+2
Avoid one level of indirection. Update #4202.
2020-12-16bsps: Add GICv3 arm_gic_irq_processor_count()Sebastian Huber2-0/+34
Update #4202.
2020-12-11bsps/gicv3: Resolve build warnings on 64bitKinsey Moore1-2/+2
2020-12-10bsps: Remove ARM GIC SGI target filterSebastian Huber2-15/+3
Remove the target filter for software-generated interrupts since this feature is not supported by the affinity routing in GICv3. Update #4202.
2020-12-10bsps: Fix GICv3 arm_gic_trigger_sgi()Sebastian Huber2-3/+3
Use the targets parameter to determine the targets of the SGI. Change targets parameter type to 32-bit to ease the parameter passing. GICv3 supports up to 16 targets. Update #4202.
2020-12-09bsps: Add SMP support to ARM GICv3Sebastian Huber1-23/+33
Update #4202.
2020-12-02bsps: Move ARM GICv2 driver to bsps/sharedKinsey Moore2-1/+276
This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
2020-10-05bsps: Break out AArch32 GICv3 supportKinsey Moore1-0/+354
This breaks out AArch32-specific code so that the shared GICv3 code can be reused by other architectures.
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