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2024-04-16dev/irq: Improve Doxgyen group assignmentsSebastian Huber1-2/+3
Make the GIC interrupt controller support a subgroup of the generic interrupt controller support.
2024-04-16bsps/arm: Improve GICv2 supportSebastian Huber1-5/+20
In addtion to 1023, the GICC_IAR register may return 1022 as a special value. Simply check for a valid interrupt vector for the dispatching. Check the GICC_IAR again after the dispatch to quickly process a next interrupt without having to go through the interrupt prologue and epiloge.
2024-04-09bsps: Include <rtems/score/processormaskimpl.h>Sebastian Huber1-0/+1
This fixes commit b678a199e499b6c3f0b453393434aefaee180423 for SMP configurations.
2024-03-27bsps: Move declarations to <bsp/irq-generic.h>Sebastian Huber1-1/+2
Move declarations of bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() to <bsp/irq-generic.h>. Canonicalize the <bsp/irq.h> includes. Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if needed (usually RTEMS_SMP). Provide stub implementations for i386 to fix build errors.
2024-03-20dev/irq: Optional arm_gic_irq_processor_count()Sebastian Huber1-0/+2
Provide arm_gic_irq_processor_count() only in SMP configurations.
2023-05-26bsps: Improve Doxygen file commentsSebastian Huber1-0/+8
2023-05-20Update company nameSebastian Huber1-1/+1
The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
2022-06-15bsps/shared/*: Change license to BSD-2Joel Sherrill1-3/+22
Updates #3053.
2022-03-10bsps/shared/: Scripted embedded brains header file clean upJoel Sherrill1-6/+0
Updates #4625.
2021-09-21bsps/gicv2: Allow BSPs to define IRQ attributesKinsey Moore1-34/+27
ARM's GICv2 is configurable and its attributes vary between implementations including omission of specific interrupts. This allows BSPs to accomodate those varying implementations with customized attribute sets.
2021-07-27bsps/irq: bsp_interrupt_facility_initialize()Sebastian Huber1-2/+1
Do not return a status code in bsp_interrupt_facility_initialize() since this leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG assertions in bsp_interrupt_facility_initialize() if necessary.
2021-07-26bsps/irq: Implement new directives for GICv2/3Sebastian Huber1-14/+73
Update #3269.
2021-07-26bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber1-1/+2
Return a status code for bsp_interrupt_set_affinity(). Update #3269.
2021-07-26bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber1-1/+2
Return a status code for bsp_interrupt_get_affinity(). Update #3269.
2021-07-26bsps/irq: bsp_interrupt_vector_disable()Sebastian Huber1-1/+2
Return a status code for bsp_interrupt_vector_disable(). Update #3269.
2021-07-26bsps/irq: bsp_interrupt_vector_enable()Sebastian Huber1-1/+2
Return a status code for bsp_interrupt_vector_enable(). Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_is_pending()Sebastian Huber1-0/+11
Add a default implementation which just returns RTEMS_UNSATISFIED. Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_get_attributes()Sebastian Huber1-0/+8
Add a default implementation which clears the attributes to zero and just returns RTEMS_SUCCESSFUL for valid parameters. Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_raise()Sebastian Huber1-0/+23
Add rtems_interrupt_raise_on() and rtems_interrupt_clear(). Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_vector_is_enabled()Sebastian Huber1-0/+11
Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
2020-12-23bsps: Use header file for GIC architecture supportSebastian Huber1-0/+1
This avoids a function call overhead in the interrupt dispatching. Update #4202.
2020-12-16bsps: Remove gicvx_interrupt_dispatch()Sebastian Huber1-1/+1
Avoid one level of indirection. Update #4202.
2020-12-16bsps: Add GICv3 arm_gic_irq_processor_count()Sebastian Huber1-0/+7
Update #4202.
2020-12-10bsps: Remove ARM GIC SGI target filterSebastian Huber1-6/+2
Remove the target filter for software-generated interrupts since this feature is not supported by the affinity routing in GICv3. Update #4202.
2020-12-10bsps: Fix GICv3 arm_gic_trigger_sgi()Sebastian Huber1-1/+1
Use the targets parameter to determine the targets of the SGI. Change targets parameter type to 32-bit to ease the parameter passing. GICv3 supports up to 16 targets. Update #4202.
2020-12-02bsps: Move ARM GICv2 driver to bsps/sharedKinsey Moore1-14/+3
This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
2020-10-05bsps: Break out AArch32 GICv3 supportKinsey Moore1-1/+1
This breaks out AArch32-specific code so that the shared GICv3 code can be reused by other architectures.
2020-02-24bsps/arm: Initialize priorities of PPIsSebastian Huber1-0/+6
At least on GICv1 the interrupts 0 up to including 31 are so called Peripheral Private Interrupts (PPIs). We have to initialize the priority of the PPIs on secondary processors.
2020-01-17bsps/arm/shared: Add GICv3 implementationKinsey Moore1-0/+16
This adds support for the GICv3 interrupt controller along with the redistributor to control SGIs and PPIs which wasn't present in GICv2 implementations. GICv3 implementations only optionally support memory-mapped GICC interface interaction and require system register access be implemented, so the GICC interface is accessed only through system registers.
2019-02-28bsps/arm: Add BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0Sebastian Huber1-3/+51
The following variants * GICv1 with Security Extensions, * GICv2 without Security Extensions, or * within Secure processor mode have the ability to assign group 0 or 1 to individual interrupts. Group 0 interrupts can be configured to raise an FIQ exception. This enables the use of NMIs with respect to RTEMS. BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 define. Use arm_gic_irq_set_group() to change the group of an interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is defined).
2019-02-28bsps/arm: Support GIC group 0/1Sebastian Huber1-1/+37
2018-04-23bsps: Move interrupt controller support to bspsSebastian Huber1-0/+0
This patch is a part of the BSP source reorganization. Update #3285.
2017-12-14bsps/arm: Disable all interrupts in GIC initSebastian Huber1-0/+4
2017-07-12Add interrupt vector set/get affinitySebastian Huber1-10/+14
Close #3071.
2017-06-20bsps: Improve interrupt vector enable/disable APISebastian Huber1-20/+8
Change bsp_interrupt_vector_enable() and bsp_interrupt_vector_disable() to not return a status code. Add bsp_interrupt_assert() and use it to validate the vector number in the vector enable/disable implementations.
2016-03-04score: Distribute clock tick to all online CPUsSebastian Huber1-0/+18
Update #2554.
2014-03-21Change all references of rtems.com to rtems.org.Chris Johns1-1/+1
2013-08-13bsps/arm: Use proper default priority for GICSebastian Huber1-1/+1
Some GIC implementations do not have the complete range of priorities. The upper bits are RAZ/WI in this case.
2013-05-31bsps/arm: Add SMP supportSebastian Huber1-34/+27
2013-05-06bsps/arm: Remove superfluous parameterSebastian Huber1-2/+1
2013-05-03bsp/realview-pbx-a9: New BSPSebastian Huber1-0/+174
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