| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | riscv: Add new BSP cfg variants to be built with llvm/clang | Hesham Almatary | 2019-10-27 | 8 | -0/+112 |
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| * | riscv: add freedom E310 Arty A7 bsp | Pragnesh Patel | 2019-10-23 | 1 | -0/+9 |
| | | | | | | | | Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board. Update #3785. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> | ||||
| * | bsp/riscv: Add missing BSP variant | Sebastian Huber | 2018-08-02 | 1 | -0/+9 |
| | | | | | Update #3433. | ||||
| * | bsp/riscv: Add new BSP variants | Sebastian Huber | 2018-06-27 | 5 | -0/+45 |
| | | | | | | | | The latest RISC-V tool chain introduced new multilib variants. Add corresponding BSP variants. Update #3433. | ||||
| * | bsp/riscv_generic: Rename to "riscv" | Sebastian Huber | 2018-06-27 | 7 | -0/+63 |
| Update #3433. | |||||
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index : rtems | |
| RTEMS Kernel, file-systems, drivers, BSPs, samples, and testsuite. | devel@rtems.org |
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