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* arm: Fix arm_cp15_set_translation_table_entries()Sebastian Huber2020-09-171-1/+1
| | | | | | | | In a multi-processor system we must broadcast the TLB maintenance operation to the Inner Shareable domain to ensure that the other processors update their TLB caches accordingly. Close #4068.
* bsps/arm: Add support for small pages MMUSebastian Huber2019-10-311-19/+51
| | | | | | | The small page MMU support reduces the granularity for memory settings through the MMU from 1MiB sections to 4KiB small pages. Enable it by default on the realview_pbx_a9_qemu BSP.
* arm/tlb: Fix the MP affinity check to invalidate ASIDs.Chris Johns2019-08-121-1/+9
| | | | | | - The TI's CortexA7 MP MPIDR register returns 0 Updates #3760
* arm: Select the TLB invalidate based on the core's Id variant.Chris Johns2019-07-311-6/+10
| | | | Closes #3760
* arm: Return the current handler from arm_cp15_set_exception_handlerChris Johns2019-06-281-2/+7
| | | | Closes #3762
* bsps: Move arm-cp15-set-ttb-entries.c to bspsSebastian Huber2018-04-241-0/+89
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move arm-cp15-set-exception-handler.c to bspsSebastian Huber2018-04-241-0/+56
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps/arm: Move libcpu content to bspsSebastian Huber2018-03-131-0/+137
This patch is a part of the BSP source reorganization. Update #3285.