rtems - RTEMS Kernel, file-systems, drivers, BSPs, samples, and testsuite.

	Commit message (Collapse)	Author	Files	Lines
2023-08-10	arm: Fix cache support for ARM926EJ-S	Sebastian Huber	1	-0/+26
	The ARM926EJ-S is an ARMv5T architecture processor and lacks some features of ARMv6 processors such as the ARM1176JZF-S. Close #4940.
2023-05-20	Update company name	Sebastian Huber	1	-1/+1
	The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
2022-07-08	bsps/arm/shared: Change license to BSD-2	Joel Sherrill	1	-3/+22
	Updates #3053.
2020-12-10	arm/cache-cp15: Support Armv8	Sebastian Huber	1	-13/+12
	Update #4202.
2018-12-21	bsps/arm: Add cache size support for CP15	Sebastian Huber	1	-0/+41

2018-12-21	bsps/arm: Add ARMv7-AR disable data cache	Sebastian Huber	1	-7/+7
	Close #3667.
2018-12-21	ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS	Sebastian Huber	1	-2/+1
	Remove this superfluous define. Update #3667.
2018-01-31	bsps: Rework cache manager implementation	Sebastian Huber	1	-5/+2
	The previous cache manager support used a single souce file (cache_manager.c) which included an implementation header (cache_.h). This required the use of specialized include paths to find the right header file. Change this to include a generic implementation header (cacheimpl.h) in specialized source files. Use the following directories and files: * bsps/shared/cache * bsps/@RTEMS_CPU@/shared/cache * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c Update #3285.
2016-07-20	arm/bsps: CP15 and basic cache support entire cache clean for more ↵	Pavel Pisa	1	-3/+19
	architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4).
2016-07-12	Misc: Spell length correctly	Joel Sherrill	1	-1/+1

2016-07-05	bsps/arm: Fix basic cache support for SMP	Sebastian Huber	1	-8/+8

2016-07-04	bsps/arm: basic on core cache support changed to use l1 functions.	Pavel Pisa	1	-3/+40
	The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem.
2016-07-04	bsps/arm: Change code to explicit selection of cache implementation for ARM ↵	Pavel Pisa	1	-0/+134
	BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support