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2024-04-16dev/irq: Improve Doxgyen group assignmentsSebastian Huber1-2/+11
Make the GIC interrupt controller support a subgroup of the generic interrupt controller support.
2024-04-16bsps/arm: Improve GICv2 supportSebastian Huber1-4/+6
In addtion to 1023, the GICC_IAR register may return 1022 as a special value. Simply check for a valid interrupt vector for the dispatching. Check the GICC_IAR again after the dispatch to quickly process a next interrupt without having to go through the interrupt prologue and epiloge.
2023-11-28bsps/imx*: imx_gpio from pointer to fdt propertyChristian Mauderer1-0/+26
Device trees allow mixing different kinds of GPIOs in one property. For that it is usefull to only provide a pointer to an arbitrary location in the property and initialize a GPIO from that.
2023-07-28bsps/arm: fix nested extern decl. warnings brought by CMSIS files updateKarel Gardas1-0/+11
2023-07-21bsps/arm: replace CMSIS v4 with CMSIS v5 filesKarel Gardas10-4360/+6113
CAVEAT: license change from BSD to Apache2 license! Explanation: The imported files come from CMSIS v5 project available on: https://github.com/ARM-software/CMSIS_5/tree/develop The files imported are located inside the CMSIS/Core/Include project sub-directory. The project does not provide any NOTICE file in its root directory nor in the directory of the imported files. The NOTICE file and its usage in the Apache 2 license was/is so far the only issue mentioned in discussion of RTEMS developers/users when considering inclusion of the code under Apache 2 license into the RTEMS project. Since the CMSIS v5 project is free from this legal hinder, we may freely use it and update files to the latest version. Technical: the patch replaces code from 2015 with the latest version which brings quite a lot of bug fixes and most importantly opens possibilities to support MCUs based on new ARM cores.
2023-05-26bsps/arm: Improve Doxygen groupsSebastian Huber4-9/+53
2023-05-26bsps: Improve Doxygen file commentsSebastian Huber1-0/+11
2023-05-20Update company nameSebastian Huber20-20/+20
The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
2022-09-22bsps/arm: Move bsp_start_hook_0_done()Sebastian Huber1-0/+6
Declare bsp_start_hook_0_done() in <bsp/start.h>.
2022-07-08bsps/arm/include: Change license to BSD-2Joel Sherrill17-51/+374
Updates #3053.
2022-05-30bsps/arm: add CMSIS Cortex-M4 Core Peripheral Access Layer Header FileKarel Gardas1-0/+1937
2022-03-10bsps/arm/: Scripted embedded brains header file clean upJoel Sherrill19-114/+1
Updates #4625.
2021-05-02bsps: Support RTEMS_NOINIT in linkcmdsSebastian Huber2-1/+9
Update #3866.
2021-04-29bsps/arm: ARMV7_CP15_START_WORKSPACE_ENTRY_INDEXSebastian Huber1-1/+1
Change the ARMV7_CP15_START_WORKSPACE_ENTRY_INDEX value to be in line with the workspace entry in ARMV7_CP15_START_DEFAULT_SECTIONS. Close #4395.
2020-12-23bsps/arm: Rely on initialized vector tableSebastian Huber1-5/+4
The arm_cp15_set_exception_handler() is a complicated function which should be avoided if possible. Update #4202.
2020-12-23bsps: Use header file for GIC architecture supportSebastian Huber1-0/+68
This avoids a function call overhead in the interrupt dispatching. Update #4202.
2020-12-23bsps/arm: Add arm-data-cache-loop-set-way.hSebastian Huber1-0/+96
This makes it possible to reuse this loop. Update #4202.
2020-12-23bsps/arm: Remove optional start hook argumentsSebastian Huber1-11/+2
The start hook arguments are not used by a BSP. Removing them avoids the need for a stack during the very early system initialization. Update #4202.
2020-12-23bsps/arm: Invalidate branch predictors earlierSebastian Huber1-2/+0
Make sure the branch predictors are invalidated before the first branch is executed. Update #4202.
2020-12-23bsps/arm: Set VBAR in start.SSebastian Huber2-79/+4
Set the VBAR to the vector table in the start section before bsp_start_hook_0() is called to earlier handle exceptions in RTEMS. Set the VBAR to the normal vector table in start.S for the main processor. Secondary processors set it in bsp_start_hook_0(). Update #4202.
2020-12-15bsps/arm: Fix MMU configurationSebastian Huber2-0/+8
Update #4184.
2020-12-14bsps/arm/imx*: Fix location of shared headersChristian Mauderer4-0/+355
When moving the headers from the imx BSP to the shared area, the wrong directory has been selected. This patch fixes that problem. Update #4180
2020-12-11bsps/arm: Fix MMU small pages supportJan Sommer1-1/+1
- For small tables only round to the next 4kiB instead of 1MiB Close #4184.
2020-12-02bsps: Move zynq-uart to bsps/sharedKinsey Moore2-241/+0
This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to accomodate use by AArch64 BSPs.
2020-10-16bsps/arm: Add workaround for Errata 794072Sebastian Huber1-0/+16
Add a workaround for Cortex-A9 Errata 845369: A short loop including a DMB instruction might cause a denial of service on another which executes a CP15 broadcast operation. Close #4115.
2020-10-16bsps/arm: Workaround for Errata 845369Sebastian Huber1-0/+15
Add a workaround for Cortex-A9 Errata 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption. Update #4115.
2020-10-05bsps: Break out AArch32 GICv3 supportKinsey Moore5-687/+1
This breaks out AArch32-specific code so that the shared GICv3 code can be reused by other architectures.
2020-10-05Move ARM PL011 UART driverKinsey Moore2-181/+0
This UART driver is now needed for BSPs other than ARM.
2020-09-17bsps/arm: Use RTEMS_SECTION()Sebastian Huber1-6/+12
2020-01-17bsps/arm/shared: Add GICv3 implementationKinsey Moore2-9/+82
This adds support for the GICv3 interrupt controller along with the redistributor to control SGIs and PPIs which wasn't present in GICv2 implementations. GICv3 implementations only optionally support memory-mapped GICC interface interaction and require system register access be implemented, so the GICC interface is accessed only through system registers.
2020-01-07bsps/arm: Define index of the workspace entry.Christian Mauderer1-0/+2
The imx BSP contained a hack to change the workspace entry of the MMU table. This makes the used define visible for other BSPs too so that the same hack can be used for example in raspberry pi too.
2019-10-31bsps/arm: Add support for small pages MMUSebastian Huber1-9/+48
The small page MMU support reduces the granularity for memory settings through the MMU from 1MiB sections to 4KiB small pages. Enable it by default on the realview_pbx_a9_qemu BSP.
2019-06-29bsp/beagle: Partial re-write of I2C driver.Christian Mauderer1-11/+24
The old driver worked well for EEPROMS with the RTEMS EEPROM driver. But it had problems with a lot of other situations. Although it's not a direct port, the new driver is heavily modeled after the FreeBSD ti_i2c driver. Closes #3764.
2019-04-11bsp/zynq-uart: Move Zynq UART driver to shared directoryJeff Kubascik2-0/+241
This driver will be shared with the xilinx-zynqmp BSP. Update #3682.
2019-04-09bsps/arm: Optimize ARMv7-M CPU counterSebastian Huber1-4/+5
Update #3456.
2019-04-09bsps/arm: Fix ARMv7-M CPU counterSebastian Huber1-0/+1
Read the current counter value again after we know that we had an underflow. Update #3456.
2019-03-08bsps/arm: Adjust CMSIS Doxygen groupsSebastian Huber4-0/+7
Update #3706.
2019-03-08bsps: Adjust shared Doxygen groupsSebastian Huber16-16/+16
Update #3706.
2019-03-08bsps: Adjust bsp.h Doxygen groupsSebastian Huber5-10/+10
Update #3706.
2019-02-28bsps/arm: Add BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0Sebastian Huber1-0/+3
The following variants * GICv1 with Security Extensions, * GICv2 without Security Extensions, or * within Secure processor mode have the ability to assign group 0 or 1 to individual interrupts. Group 0 interrupts can be configured to raise an FIQ exception. This enables the use of NMIs with respect to RTEMS. BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 define. Use arm_gic_irq_set_group() to change the group of an interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is defined).
2019-02-28bsps/arm: Fix typoSebastian Huber1-1/+1
2019-02-28bsps/arm: Support GIC group 0/1Sebastian Huber3-4/+54
2019-02-28Remove explicit file names from @fileSebastian Huber7-7/+7
This makes the @file documentation independent of the actual file name. Update #3707.
2019-02-27arm/beagle: SPI driverPierre-Louis Garnier1-1/+92
2018-08-20bsps/arm: Fix PL111 register define re-definitionSebastian Huber1-1/+1
Close #3502.
2018-07-25_SMP_Start_multitasking_on_secondary_processor()Sebastian Huber1-1/+1
Pass current processor control as first parameter to make dependency more explicit.
2018-07-24bsps: Fix function declaration warningsSebastian Huber1-2/+2
2018-07-05bsps/arm: Include missing header fileSebastian Huber1-0/+1
2018-06-27Rework initialization and interrupt stack supportSebastian Huber1-22/+1
Statically initialize the interrupt stack area (_Configuration_Interrupt_stack_area_begin, _Configuration_Interrupt_stack_area_end, and _Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the interrupt stack area in a special section ".rtemsstack.interrupt". Let BSPs define the optimal placement of this section in their linker command files (e.g. in a fast on-chip memory). This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the low level initialization code has all information available via global symbols. This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define superfluous, since the interrupt stacks are allocated by confdefs.h for all architectures. There is no need for BSP-specific linker command file magic (except the section placement), see previous ARM linker command file as a bad example. Remove _CPU_Install_interrupt_stack(). Initialize the hardware interrupt stack in _CPU_Initialize() if necessary (e.g. m68k_install_interrupt_stack()). The optional _CPU_Interrupt_stack_setup() is still useful to customize the registration of the interrupt stack area in the per-CPU information. The initialization stack can reuse the interrupt stack, since * interrupts are disabled during the sequential system initialization, and * the boot_card() function does not return. This stack resuse saves memory. Changes per architecture: arm: * Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases. * Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp. bfin: * Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value. lm32, m32c, mips, nios2, riscv, sh, v850: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. m68k: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. powerpc: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. * Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA). sparc: * Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM. Update #3459.
2018-06-15arm: Simplify CPU counter supportSebastian Huber1-0/+78
Use the standard ARMv7-M systick module for the ARMv7-M CPU counter instead of DWT counter since the DWT counter is affected by power saving states. Use an inline function for _CPU_Counter_difference() for all ARM BSPs. Update #3456.
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