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2023-05-20Update company nameSebastian Huber1-1/+1
The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
2022-07-08bsps/arm/altera-cyclone-v: Change license to BSD-2Joel Sherrill1-3/+22
Updates #3053.
2022-03-10bsps/arm/: Scripted embedded brains header file clean upJoel Sherrill1-6/+0
Updates #4625.
2019-03-04bsp/altera-cyclone-v: Adjust Doxygen file groupsSebastian Huber1-0/+6
Update #3707.
2018-04-20bsps: Move console drivers to bspsSebastian Huber1-0/+0
This patch is a part of the BSP source reorganization. Update #3285.
2018-01-04bsp/altera-cyclone-v: Use public include pathChris Johns1-4/+4
Update #3254.
2017-09-12Simplify and unify BSP_output_charSebastian Huber1-4/+0
The BSP_output_char should output a char and not mingle with high level processing, e.g. '\n' to '\r\n' translation. Move this translation to rtems_putc(). Remove it from all the BSP_output_char implementations. Close #3122.
2016-06-24bsps: Include missing <rtems/bspIo.h>Sebastian Huber1-0/+2
2015-04-02bsp/altera-cyclone-v: Fix define usageSebastian Huber1-1/+1
2014-10-07libchip/serial: Add alternative NS16550 driverSebastian Huber1-90/+69
Use the Termios device API.
2014-09-10bsp/altera-cyclone-v: Add BSP_USE_UART_INTERRUPTSSebastian Huber1-3/+9
2014-05-12bsp/altera-caclone-v: Early printk supportRalf Kirchner1-24/+4
Make sure printk can work early during BSP startup.
2014-03-21Change all references of rtems.com to rtems.org.Chris Johns1-1/+1
2014-03-13bsp/altera-cyclone-v: New BSPRalf Kirchner1-0/+195
Implemented so far: - nocache heap for uncached RAM - basic timer - level 1 cache handling for arm cache controller in arm-cache-l1.h - level 2 L2C-310 cache controller - MMU - DWMAC 1000 ethernet controller - basic errata handling - smp startup for second core