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* kern_tc.c: Update pps_event() for uniprocessor configurationsGabriel Moyano2022-06-101-0/+6
| | | | | | Since pps->capgen equal to zero is not a special value in uniprocessor configurations, there is no need to check for this condition. Update #2349
* bsps/imx: Enable clock of ETH2Christian Mauderer2022-06-093-0/+173
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* Newlib01: Add tests for rand() and lrand48()Matt Joyce2022-06-092-0/+53
| | | | | | Check that the state of rand() and lrand48() is thread-specific, that they are properly initialized, and return the expected sequence of pseudo-random numbers for default seed values.
* testsuite/libtests: Add exit03 to test exit() with C++Chris Johns2022-06-096-0/+221
| | | | Updates #4661
* arm/lpc32xx: Implement new interrupt directivesSebastian Huber2022-06-081-6/+42
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* bsp/lpc32xx: bsp_interrupt_vector_enable()Sebastian Huber2022-06-081-2/+6
| | | | | | | | The interrupt enables are used to implement a priority scheme in bsp_interrupt_dispatch(). Enable interrupts through bsp_interrupt_vector_enable() only if they are not already enabled to not interfere with the priority scheme while bsp_interrupt_vector_enable() is called during interrupt dispatching.
* bsp/lpc32xx: bsp_interrupt_is_valid_vector()Sebastian Huber2022-06-082-0/+31
| | | | | Provide custom bsp_interrupt_is_valid_vector() implementation since several interrupt vectors are reserved.
* bsp/lpc32xx: Use standard timer 2 for tm27.hSebastian Huber2022-06-081-19/+39
| | | | | This helps to run the validation tests of the Interrupt Manager directives.
* arm/lpc32xx: Hide MLC detailsSebastian Huber2022-06-081-3/+1
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* bsp/lpc32xx: Fix FIQ interrupt supportSebastian Huber2022-06-081-10/+13
| | | | | Do not sporadically service interrupts configured as FIQ by the IRQ interrupt dispatch.
* validation: Fix CallWithinISR()Sebastian Huber2022-06-081-0/+2
| | | | | | | Some BSPs require that Clear_tm27_intr() is called in the interrupt service routine. Update #3269.
* arm: Fix PMSA regions for contiguous sectionsSebastian Huber2022-06-081-4/+4
| | | | | | | | | | Sections with identical attributes may be contiguous with a respective begin and end address which is not on a minimum region boundary. The begin address is aligned down to the region base address. The end address is aligned up to the region end address. Account for this in the check for contiguous sections. Update #4202.
* arm: Fix PMSA region mapping with 0x0 end addressSebastian Huber2022-06-081-1/+1
| | | | | | | | A section may span up to the end of the address range. In this case the end address is zero. Use the base address to check if a region should be before another region. Update #4202.
* build: Assert value properties only if not NoneSebastian Huber2022-06-081-9/+9
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* bsps/atsam: Fix type of optionsChristian Mauderer2022-06-072-4/+4
| | | | | | ATSAM_CONSOLE_DEVICE_INDEX and ATSAM_CONSOLE_DEVICE_TYPE have to be integers like suggested by their description. Otherwise it's not possible to select (for example) USART2 as console device.
* arm: Fix typoSebastian Huber2022-06-031-2/+2
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* bsps/stm32h7: set SDRAM 1 size to 0 by default on nucleo-h743zi BSPKarel Gardas2022-06-021-0/+1
| | | | | | | Nucleo does not have any SDRAM, so 0 size is the only possible right choice here. Sponsored-By: Precidata
* bsps/stm32h7: set default linkage to flash for nucleo-h743zi BSPKarel Gardas2022-06-021-0/+1
| | | | | | | Nucleo does not have any SDRAM so default linkage to SDRAM does not make any sense here. Sponsored-By: Precidata
* bsps/stm32h7: set default printk instance on nucleo-h743zi BSP to USART3Karel Gardas2022-06-021-1/+4
| | | | | | | | This is the default configuration of the board out of the box. Any other possible/supported configuration requires soldering, so definitely not out of the box experience. Sponsored-By: Precidata
* bsps/stm32h7: add stm32h747i-disco-m4 BSP variantKarel Gardas2022-06-0220-0/+43
| | | | | | | | | This patch adds stm32h747i-disco-m4 BSP variant and puts it in sync with the stm32h747i-disco BSP variant hardware support. That means, only USART 1, 2 and UART 8 are enabled. Also SDRAM 2 is set to 32MB, SDRAM 1 size is set to 0. Sponsored-By: Precidata
* bsps/stm32h7: set default SDRAM x sizes on stm32h747i-disco BSPKarel Gardas2022-06-012-0/+2
| | | | | | | | | This means: SDRAM 1: 0 SDRAM 2: 32 MB Sponsored-By: Precidata
* bsps/stm32h7: disable all unsupported U(S)ARTs on stm32h747i-disco BSPKarel Gardas2022-06-017-0/+7
| | | | | | | | This patch disables all U(S)ARTs which are not supported by the board itself and its provided connectors. That means only USART1 and 2 and UART8 are enabled. Sponsored-By: Precidata
* bsps/stm32h7: add configuration and enable build of stm32h747i-disco BSPKarel Gardas2022-06-018-0/+33
| | | | Sponsored-By: Precidata
* bsps/stm32h7: add board C files for stm32h747i-disco BSPKarel Gardas2022-06-014-0/+736
| | | | | | | | | | | | Besides C files for the BSP variant the patch also provides license clarification on system_stm32h7xx.c file which is provided in boards/stm/stm32h747i-disco directory. The files comes from STM32CubeH7 project and references "root directory" in its license comment and it's not clear where this points out. Let's add clarification comment about it and also based on it and resulting license let's add SPDX license identifier. Sponsored-By: Precidata
* bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval-m4 BSPKarel Gardas2022-06-012-0/+2
| | | | | | | | | This means: SDRAM 1: 0 SDRAM 2: 32 MB Sponsored-By: Precidata
* bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval-m4 BSPKarel Gardas2022-06-019-0/+9
| | | | | | | This patch disables all U(S)ARTs which are not supported by the board itself and its provided connectors. Sponsored-By: Precidata
* bsps/stm32h7: add configuration and enable build of stm32h757i-eval-m4 BSPKarel Gardas2022-06-0111-3/+66
| | | | | | | | | | | | | | | | This is minimalist configuration for the stm32h757i-eval-m4 BSP provided here. The only general enhancement worth mention is a flash origin address configuration which is needed for simplification as M4 core boots from second flash bank which starts at 0x8100000 by default. The boot address of the core may be changed by using STM32CubeProgrammer. If done so then also BSP configuration needs to be changed accordingly. As the BSP variant is running on M4 core, there is also more configuration changes required here. E.g. boot core and ABI (compilation flags) in comparison with stm32h757i-eval BSP. On the other hand, C code is shared completely with this BSP variant. Sponsored-By: Precidata
* bsps/stm32h7: include CMSIS Cortex-M4 header when required by configurationKarel Gardas2022-06-011-0/+7
| | | | Sponsored-By: Precidata
* bsps/stm32h7: move cache implementation from obj to BSPs own yml fileKarel Gardas2022-06-015-1/+4
| | | | | | | This is done in preparation for future Cortex-M4 based BSP variants which do not provide cache at all. Sponsored-By: Precidata
* bsps/stm32h7: enable cache and MPU only on Cortex-M7Karel Gardas2022-06-011-0/+4
| | | | Sponsored-By: Precidata
* bsps/arm: add CMSIS Cortex-M4 Core Peripheral Access Layer Header FileKarel Gardas2022-05-301-0/+1937
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* bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval BSPKarel Gardas2022-05-272-1/+5
| | | | | | | | | This means: SDRAM 1: 0 SDRAM 2: 32 MB Sponsored-By: Precidata
* bsps/stm32h7: enable SDRAM 2 MPU regionKarel Gardas2022-05-271-0/+7
| | | | Sponsored-By: Precidata
* bsps/stm32h7: provide linkcmds for SRAM, FLASH_SDRAM and SRAM_SDRAM linkingKarel Gardas2022-05-275-2/+156
| | | | Sponsored-By: Precidata
* bsps/stm32h7: add and enable test set exclusion for stm32h757i-eval BSPKarel Gardas2022-05-272-0/+21
| | | | Sponsored-By: Precidata
* bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval BSPKarel Gardas2022-05-279-2/+16
| | | | | | | This patch disables all U(S)ARTs which are not supported by the board itself and its provided connectors. Sponsored-By: Precidata
* bsps/stm32h7: add configuration and enable build of stm32h757i-eval BSPKarel Gardas2022-05-277-0/+54
| | | | | | | | | | This is minimalist configuration for the stm32h757i-eval BSP provided here. The only general enhancement worth mention is boot core configuration which is needed here as this is the first dual-core board supported by stm32h7 BSP family and we need to choose boot core in order to get C files compiling well. Sponsored-By: Precidata
* bsps/stm32h7: add board C files for stm32h757i-eval BSPKarel Gardas2022-05-274-0/+976
| | | | | | | | | | | | Besides C files for the BSP variant the patch also provides license clarification on system_stm32h7xx.c file which is provided in boards/stm/stm32h757i-eval directory. The files comes from STM32CubeH7 project and references "root directory" in its license comment and it's not clear where this points out. Let's add clarification comment about it and also based on it and resulting license let's add SPDX license identifier. Sponsored-By: Precidata
* sppps01: Improve default handler testGabriel Moyano2022-05-271-0/+6
| | | | Update #2349.
* score: Fix pps_fetch()Sebastian Huber2022-05-271-1/+2
| | | | | | Return early only if there was a timeout, otherwise return the PPS info. Update #2349.
* MAINTAINERS: Add myself to Write After ApprovalKarel Gardas2022-05-261-1/+2
| | | | Add myself also to Localized Write Permission for x86_64.
* score: Reformat for code coverageSebastian Huber2022-05-231-2/+18
| | | | Close #2349.
* testsuites/sptests: Add sppps01 testGabriel Moyano2022-05-233-0/+212
| | | | Update #2349.
* timecounter.h: Add _Timecounter_Discipline()Gabriel Moyano2022-05-232-0/+26
| | | | Update #2349.
* timepps.h: PPS_SYNC defined by defaultGabriel Moyano2022-05-233-11/+2
| | | | Update #2349.
* kern_ntptime.c: Add define in order to remove warningGabriel Moyano2022-05-231-0/+3
| | | | Update #2349.
* kern_tc.c: Enable PPS API supportGabriel Moyano2022-05-231-4/+0
| | | | Update #2349.
* kern_tc.c: Add definitions required by PPS APIGabriel Moyano2022-05-231-0/+6
| | | | Update #2349.
* score: Rename tc_getfrequency()Gabriel Moyano2022-05-233-1/+19
| | | | | | Rename tc_getfrequency() to _Timecounter_Get_frequency(). Update #2349.
* kern_tc.c: Replace FreeBSD event mechanism by adding pointers to functionGabriel Moyano2022-05-232-0/+65
| | | | Update #2349.