| Commit message (Collapse) | Author | Age | Files | Lines |
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This avoids a dependency on the non-standard libxml2 module. Reorder
test cases according to expected performance.
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This avoids a dependency on the non-standard libxml2 module.
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Use a SPARC-specific method to flush the register windows. This
improves the timing measurements.
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The previous method to prevent optimizations no longer worked at least
with GCC 13. Disable intra-procedural optimizations.
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This cleans up outputUsesInterrupts usage with rtems_termios_device_mode
enum values. The outputUsesInterrupts member was typed as an int, named
as if it were a boolean value, and used as if it were a
rtems_termios_device_mode enum. In this patch, values assigned to
outputUsesInterrupts have been converted to the corresponding
rtems_termios_device_mode enum value, conversions from
deviceOutputUsesInterrupts have been made explicit, and uses of
rtems_termios_device_mode enum values with deviceOutputUsesInterrupts
have been converted to booleans.
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When the CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS definition was added
to AArch64 cache management, it obsoleted the *_1_data/instruction_line
functions. These have been removed since they are no longer referenced.
The AArch64_instruction_cache_inner_shareable_invalidate_all function is
only used when RTEMS_SMP is defined, so only define it in that
circumstance.
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When encountering an error during filesystem creation, fat_fd must be
cleaned up appropriately once the file is opened. There was an
opportunity for a resource leak due to jumping to the incorrect error
handling label.
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This reverts commit d1d3ceb502cf4075c28a052b36630125387e1026.
Per discussions on devel@ and Discord.
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An error is already being reported. Checking the return value of this
function is not useful.
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This adds a second set of JFFS2 tests running on top of a simulated NAND
backend to ensure that interactions with delayed writes operate as
expected.
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Revert JFFS2 to non-granular locking. This makes the superblock
available to the delayed work that it owns so that delayed work
processing can ensure that shared resources are being exclusively
accessed. This change only affects NAND systems. Moving forward with
granular locking will require a significant investment of time in
producing a test harness that doesn't require hardware such that this
can get a reasonable amount of test coverage.
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A verbose verbosity is not required for normal test suite runs. It may
be used to debug test cases.
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Document CONFIGURE_JFFS2_DELAYED_WRITE_TASK_PRIORITY.
Update #4961.
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The TM27 support may define TM27_INTERRUPT_VECTOR_ALTERNATIVE to provide
an alternative software generated interrupt request which is raised by
_TM27_Raise_alternative() and cleared by _TM27_Clear_alternative().
Both functions shall return an RTEMS status code. This interrupt vector
may be used to test the interrupt controller support on targets which do
not provide generic software generated interrupts.
Update #3716.
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Let the BSP define TM27_INTERRUPT_VECTOR_DEFAULT to more efficiently and
reliably get the TM27 default interrupt vector.
Update #3716.
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Expose functions to directly manipulate the bad block table (BBT). These
functions are necessary to correct possible BBT corruption caused by
bugs in the BBT management layer.
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The XNandPsu_EraseBlock function takes a target device and a block
offset for erasure. Ensure the block offset is within the size of the
target device.
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When marking the trailing blocks on a device as reserved for Bad Block
Table usage, ensure that the correct blocks are marked. This resolves an
off-by-one error that was marking one block too low and leaving the last
block in the device unmarked.
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When writing out the Bad Block Table, write it to the targeted device
and ensure the block is appropriately mapped to the targeted device.
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Mark the BBT descriptor as invalid before scanning to ensure that
missing BBTs are detected and written correctly if necessary.
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The Bad Block Table is a per-device catalog of the dispositions of each
block in the device. Only read enough data to determine the dispositions
of blocks for the device being read.
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The xnandpsu driver includes functionality to map back and forth between
the flash-based BBT and the memory-based BBT with the values in each
being a bitwise inversion of each other. This resolves several bugs in
this process and simplifies the inversion from operating on the block
representation to operating on the entire BBT entry (4 blocks, 2 bits
per block, one byte total).
Bugs resolved in XNandPsu_ConvertBbt():
* The calculation of memory BBT entry offset was off by a factor of 4
* The entry offset into the flash BBT has been removed since each flash
BBT directly describes the flash space it is contained within and has
no reference to other devices in the chip
Bugs resolved in XNandPsu_WriteBbt():
* The BBT length calculated was reduced to NumTargetBlocks from
NumBlocks since only the relevant portion of the in-memory BBT should
be written to the flash-based BBT space
* An offset was applied to values retrieved from the in-memory BBT so
that only the relevant portion was converted and written to the
flash-based BBT
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The XNandPsu_IsBlockBad() function is insufficient for JFFS2 to
determine whether a block is usable since the function does not report
reserved blocks. JFFS2 is also unable to use the last 4 blocks of each
target attached to the NAND controller since they are reserved for the
Bad Block Table (BBT), but not necessarily marked as such.
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Hi all, this is my first email patch submission and my first contribution to RTEMS, so please give any
feedback you have!
This patch enables interrupt driven data reception on USART ports on
STM32F4 series chips. This feature is gated behind the config flag
BSP_CONSOLE_USE_INTERRUPTS. If this flag is not set to True, the older
polling implementation will be used. I tested this feature on STM32F401CE
(blackpill) and STM32 Nucleo F411RE boards, with both capable of keeping
up with a 115200 baud continous data stream. With the older polling
implementation, both would drop bytes at 9600 baud. In addition, I
updated the implementation of usart_set_attributes to support changing
the baud rate of the USART port based on the input speed.
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Route the test output through T_vprintf() only while the test suite
runs. Otherwise, the begin/end of test message may not show up.
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Route the test output through T_vprintf().
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This feature is not supported by lwIP.
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- Extend the timeout to 150 msec for long remote sessions
- Improve the performance of the detection
Closes #4975
Closes #4977
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Place the vector table in the start section so that the overlay can be
avoided if we execute from internal flash. The problem is that when the
POM is enabled, the ECC cannot be enabled for the internal flash.
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Replace TMS570_MMR_SELECT_GMII_SEL with TMS570_MMR_SELECT_MII_MODE and
TMS570_MMR_SELECT_RMII_MODE.
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Rearrange pin function bit fields to allow the clearing of all function
bits through TMS570_PIN_AND_FNC().
Move implementation details to source file.
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Add the BSP option BSP_START_VECTOR_ADDRESS_TABLE_ALIGNMENT to
optionally define an alignment of the vector address table begin.
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This patch adds basic support for the following boards:
xilinx_zynq_pynq - PYNQ Z1 / Z2
xilinx_zynq_microzed - MicroZed 7010 / 7020
xilinx_zynq_picozed - PicoZed 7010 / 7015 / 7020 / 7030
xilinx_zynq_zybo - ZYBO
xilinx_zynq_zybo_z7 - ZYBO Z7-10 / Z7-20
N.b. Arty Z7-20 is basically a PYNQ Z1 - different board
color and updated Eth PHY.
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