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* Documented the following Event Logging routines:Wade A Smith1998-08-101-48/+172
* Documented the dump_setpath function.Wade A Smith1998-08-101-4/+22
* Added documentation for the following Configuration Space Operations:Wade A Smith1998-08-101-46/+342
* Reordered some stuff.Joel Sherrill1998-08-081-7/+10
* changed version to 980808Joel Sherrill1998-08-082-2/+2
* Corrected spacing.Joel Sherrill1998-08-081-1/+1
* Changed debug level.Joel Sherrill1998-08-082-36/+96
* changed version to 9800808Joel Sherrill1998-08-082-2/+2
* Removed SonicRegisters structure since we now use register indicesJoel Sherrill1998-08-061-83/+15
* Enabled specific types of debug info.Joel Sherrill1998-08-061-31/+55
* Changed debug enable macros to support individually enabling differentJoel Sherrill1998-08-061-15/+30
* Card Resource Register was a 16-bit register not a 32-bit one.Joel Sherrill1998-08-065-28/+36
* Added support for the Card Resource Register. The new probe routinesJoel Sherrill1998-08-065-8/+107
* Commented out the code which yields the CPU when the serial controller isJoel Sherrill1998-08-056-0/+12
* Added constants which made the multiple bit settings more readableJoel Sherrill1998-08-051-0/+25
* DCR setting changed to match what the DY-4 Firmware initialized it to.Joel Sherrill1998-08-051-135/+259
* Patch from Eric Valette <valette@crf.canon.fr> which brings the i386ex BSPJoel Sherrill1998-08-0527-578/+379
* changed load addressJoel Sherrill1998-08-051-2/+5
* Automatic CPU type detection code from Eric Valette <valette@crf.canon.fr>.Joel Sherrill1998-08-0517-30/+698
* Fixed name of Buffer so this would compile.Joel Sherrill1998-08-051-3/+3
* Redid Makefiles to properly do a preinstall. There was remnants of theJoel Sherrill1998-08-0511-62/+20
* Added print of the order in which the directories are preinstalled.Joel Sherrill1998-08-051-1/+9
* More complete shells generated.Joel Sherrill1998-08-0418-277/+1245
* Switched to read/write register routines and added some basic debugJoel Sherrill1998-08-032-332/+473
* Added many new chaptersJoel Sherrill1998-08-0318-15/+3791
* Under allcoated task stacks.Joel Sherrill1998-08-032-2/+2
* Changed to be posix users "new"Joel Sherrill1998-08-011-2/+4
* Added files and directories.Joel Sherrill1998-08-011-1/+9
* Fixed to add files and directories.Joel Sherrill1998-08-011-7/+13
* Added process and procenv.Joel Sherrill1998-08-011-3/+15
* Added language variables.Joel Sherrill1998-08-011-1/+14
* Now generates complete template for chapters.Joel Sherrill1998-08-011-53/+85
* New files -- automatically gnerated templates.Joel Sherrill1998-08-012-0/+722
* New fileJoel Sherrill1998-08-011-0/+65
* Removed items which are now automatically generated.Joel Sherrill1998-08-011-41/+1
* New file.Joel Sherrill1998-08-011-0/+98
* Removed all node and menu information since this information is nowJoel Sherrill1998-08-019-563/+12
* Modified so chapters are automatically generated.Joel Sherrill1998-08-011-8/+4
* New fileJoel Sherrill1998-08-011-0/+7
* Don't automatically generate this one.Joel Sherrill1998-08-011-0/+0
* Moved to thread.t and node information automatically generatedJoel Sherrill1998-08-011-1025/+0
* Moved to signal.t and node information automatically generatedJoel Sherrill1998-08-011-691/+0
* Moved to sched.t and node information automatically generatedJoel Sherrill1998-08-011-228/+0
* Moved to preface.t and node information automatically generatedJoel Sherrill1998-08-011-21/+0
* Moved to mutex.t and node information automatically generatedJoel Sherrill1998-08-011-642/+0
* Moved to key.t and node information automatically generatedJoel Sherrill1998-08-011-179/+0
* Moved to cond.t and node information automatically generatedJoel Sherrill1998-08-011-386/+0
* Moved to clock.t and node information automatically generatedJoel Sherrill1998-08-011-264/+0
* Added automatic generation of files.Joel Sherrill1998-08-019-1/+3478
* Moved to network demosJoel Sherrill1998-08-011-8/+1