summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* bsp/x86_64: Minimal bootable BSPAmaan Cheval2018-07-1129-1/+1605
| | | | | | | | | | | | | | | | Current state: - Basic context initialization and switching code. - Stubbed console (empty functions). - Mostly functional linker script (may need tweaks if we ever want to move away from the large code model (see: CPU_CFLAGS). - Fully functional boot, by using FreeBSD's bootloader to load RTEMS's ELF for UEFI-awareness. In short, the current state with this commit lets us boot, go through the system initialization functions, and then call user application's Init task too. Updates #2898.
* bsp/riscv: Add console support for NS16550 devicesSebastian Huber2018-07-063-1/+109
| | | | Update #3433.
* bsp/riscv: Simplify printk() supportSebastian Huber2018-07-063-19/+16
| | | | | | | This is a prepartion to add NS16550 driver support to the console driver. Update #3433.
* riscv: Add LADDR assembler defineSebastian Huber2018-07-063-10/+20
| | | | | | | An address must be loaded to a register according to the code model. Add LADDR define for use in assembler code. Update #3433.
* riscv: Implement CPU counterSebastian Huber2018-07-063-12/+18
| | | | Update #3433.
* Update config.guess and config.subSebastian Huber2018-07-062-1161/+1188
| | | | | | | | | Update via: wget -O config.guess 'https://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD' wget -O config.sub 'https://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD' Update #3433.
* bsps/arm: Include missing header fileSebastian Huber2018-07-051-0/+1
|
* bsps: Update headers.amSebastian Huber2018-07-052-0/+9
|
* riscv: Clear reservationsSebastian Huber2018-07-055-6/+25
| | | | | | | See also RISC-V User-Level ISA V2.3, comment in section 8.2 "Load-Reserved/Store-Conditional Instructions". Update #3433.
* posix: Check for new <pthread.h> prototypesSebastian Huber2018-07-055-9/+40
| | | | | Update #3342. Update #3343.
* riscv: Fix fcsr initializationSebastian Huber2018-07-022-1/+19
| | | | Update #3433.
* score: Increase PER_CPU_CONTROL_SIZE_APPROXSebastian Huber2018-06-291-1/+1
| | | | | | Increase the PER_CPU_CONTROL_SIZE_APPROX on 64-bit targets. Update #3433.
* riscv: Fix SMP context switch supportSebastian Huber2018-06-291-2/+2
| | | | Update #3433.
* riscv: Add SMP context switch supportSebastian Huber2018-06-291-0/+47
| | | | Update #3433.
* riscv: Add floating-point supportSebastian Huber2018-06-298-50/+538
| | | | Update #3433.
* riscv: Fix global constructionSebastian Huber2018-06-293-6/+7
| | | | Update #3433.
* riscv: Add TLS supportSebastian Huber2018-06-292-0/+9
| | | | Update #3433.
* riscv: Remove dead codeSebastian Huber2018-06-291-41/+1
| | | | Update #3433.
* riscv: Optimize context switch and interruptsSebastian Huber2018-06-296-174/+255
| | | | | | | | Save/restore non-volatile registers in _CPU_Context_switch(). Save/restore volatile registers in _ISR_Handler(). Update #3433.
* riscv: Fix _CPU_Context_Initialize() prototypeSebastian Huber2018-06-292-12/+12
| | | | Update #3433.
* riscv: Fix interrupt save/restoreSebastian Huber2018-06-291-1/+1
| | | | Update #3433.
* riscv: Implement _CPU_Context_validate()Sebastian Huber2018-06-292-160/+168
| | | | Update #3433.
* riscv: Make some CPU port defines visible to asmSebastian Huber2018-06-292-37/+49
| | | | | | Move SREG and LREG assembler defines to <rtems/score/asm.h>. Update #3433.
* riscv: Implement _CPU_Context_volatile_clobber()Sebastian Huber2018-06-292-16/+16
| | | | Update #3433.
* riscv: Remove mstatus from thread contextSebastian Huber2018-06-294-27/+14
| | | | | | | | | | The mstatus register contains no thread-specific state which must be saved/restored during a context switch. Machine interrupts (MIE) must be enabled during a context switch. Create separate CPU_Interrupt_frame structure. Update #3433.
* riscv: Remove x8 initializationSebastian Huber2018-06-291-2/+0
| | | | | | | | | | The RISC-V psABI https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md does not mention that this is a frame pointer. Update #3433.
* riscv: Properly align the thread stackSebastian Huber2018-06-291-3/+7
| | | | Update #3433.
* riscv: Do not clear thread contextSebastian Huber2018-06-291-5/+2
| | | | | | | | Do not clear the complete thread context. Initialize only the necessary members. The Context_Control::is_executing member must be preserved across _CPU_Context_Initialize() calls. Update #3433.
* riscv: Fix CPU_STACK_ALIGNMENTSebastian Huber2018-06-291-1/+2
| | | | | | | | | | According to the RISC-V psABI https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md the stack alignment is 128 bits (16 bytes). Update #3433.
* riscv: Remove RISCV_GCC_RED_ZONE_SIZESebastian Huber2018-06-292-5/+1
| | | | | | | | | | | The current ABI says that there is no stack red zone: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md "Procedures must not rely upon the persistence of stack-allocated data whose addresses lie below the stack pointer." Update #3433.
* riscv: Enable interrupts during dispatch after ISRSebastian Huber2018-06-295-55/+91
| | | | | | | | The code sequence is derived from the ARM code (see _ARMV4_Exception_interrupt). Update #2751. Update #3433.
* riscv: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2018-06-283-1/+28
| | | | Update #3433.
* riscv: Avoid namespace pollutionSebastian Huber2018-06-284-10/+5
| | | | | | | Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h> (which is visible via <rtems.h> for example). Update #3433.
* riscv: Optimize and fix interrupt disable/enableSebastian Huber2018-06-281-15/+16
| | | | | | | | | Use the atomic read and clear operation to disable interrupts. Do not write the complete mstatus. Instead, set only the MIE bit depending on the level parameter. Update #3433.
* bsp/riscv: Remove bsp_interrupt_handler_default()Sebastian Huber2018-06-281-9/+0
| | | | | | It duplicated the default implementation. Update #3433.
* bsp/riscv: Rework clock driverSebastian Huber2018-06-284-65/+125
| | | | | | | Use device tree provided timebase frequency. Do not write to read-only mtime register. Update #3433.
* bsp/riscv: Add device tree support for consoleSebastian Huber2018-06-285-65/+222
| | | | Update #3433.
* bsp/riscv: Fix vector table for lp64Sebastian Huber2018-06-281-16/+22
| | | | Update #3433.
* bsp/riscv: Add SMP startup synchronizationSebastian Huber2018-06-281-2/+20
| | | | Update #3433.
* bsp/riscv: Add device tree supportSebastian Huber2018-06-284-6/+27
| | | | Update #3433.
* riscv: Add dummy SMP supportSebastian Huber2018-06-285-126/+42
| | | | Update #3433.
* build: Enable RISC-V SMP buildSebastian Huber2018-06-283-3/+3
| | | | Update #3433.
* riscv: Implement ISR set/get levelSebastian Huber2018-06-282-9/+18
| | | | | | Fix prototypes. Update #3433.
* bsp/riscv: Load global pointerSebastian Huber2018-06-272-2/+6
| | | | Update #3433.
* bsp/riscv: Use memset() to clear .bssSebastian Huber2018-06-271-10/+5
| | | | Update #3433.
* riscv: Format assembler filesSebastian Huber2018-06-275-468/+473
| | | | | | Use tabs to match the GCC generated assembler output. Update #3433.
* bsp/riscv: Do not clear integer registers at startSebastian Huber2018-06-271-31/+0
| | | | | | There is no need to do this. Update #3433.
* bsp/riscv: Fix some warningsSebastian Huber2018-06-271-20/+4
| | | | Update #3444.
* bsp/riscv: Add BSP options to define RAM regionSebastian Huber2018-06-272-3/+25
| | | | Update #3433.
* bsp/riscv: Remove unused BSP optionsSebastian Huber2018-06-271-10/+0
| | | | Update #3433.
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-23 16:16:23 +0000