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* bsp/x86_64: Minimal bootable BSPAmaan Cheval2018-07-1129-1/+1605
* bsp/riscv: Add console support for NS16550 devicesSebastian Huber2018-07-063-1/+109
* bsp/riscv: Simplify printk() supportSebastian Huber2018-07-063-19/+16
* riscv: Add LADDR assembler defineSebastian Huber2018-07-063-10/+20
* riscv: Implement CPU counterSebastian Huber2018-07-063-12/+18
* Update config.guess and config.subSebastian Huber2018-07-062-1161/+1188
* bsps/arm: Include missing header fileSebastian Huber2018-07-051-0/+1
* bsps: Update headers.amSebastian Huber2018-07-052-0/+9
* riscv: Clear reservationsSebastian Huber2018-07-055-6/+25
* posix: Check for new <pthread.h> prototypesSebastian Huber2018-07-055-9/+40
* riscv: Fix fcsr initializationSebastian Huber2018-07-022-1/+19
* score: Increase PER_CPU_CONTROL_SIZE_APPROXSebastian Huber2018-06-291-1/+1
* riscv: Fix SMP context switch supportSebastian Huber2018-06-291-2/+2
* riscv: Add SMP context switch supportSebastian Huber2018-06-291-0/+47
* riscv: Add floating-point supportSebastian Huber2018-06-298-50/+538
* riscv: Fix global constructionSebastian Huber2018-06-293-6/+7
* riscv: Add TLS supportSebastian Huber2018-06-292-0/+9
* riscv: Remove dead codeSebastian Huber2018-06-291-41/+1
* riscv: Optimize context switch and interruptsSebastian Huber2018-06-296-174/+255
* riscv: Fix _CPU_Context_Initialize() prototypeSebastian Huber2018-06-292-12/+12
* riscv: Fix interrupt save/restoreSebastian Huber2018-06-291-1/+1
* riscv: Implement _CPU_Context_validate()Sebastian Huber2018-06-292-160/+168
* riscv: Make some CPU port defines visible to asmSebastian Huber2018-06-292-37/+49
* riscv: Implement _CPU_Context_volatile_clobber()Sebastian Huber2018-06-292-16/+16
* riscv: Remove mstatus from thread contextSebastian Huber2018-06-294-27/+14
* riscv: Remove x8 initializationSebastian Huber2018-06-291-2/+0
* riscv: Properly align the thread stackSebastian Huber2018-06-291-3/+7
* riscv: Do not clear thread contextSebastian Huber2018-06-291-5/+2
* riscv: Fix CPU_STACK_ALIGNMENTSebastian Huber2018-06-291-1/+2
* riscv: Remove RISCV_GCC_RED_ZONE_SIZESebastian Huber2018-06-292-5/+1
* riscv: Enable interrupts during dispatch after ISRSebastian Huber2018-06-295-55/+91
* riscv: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2018-06-283-1/+28
* riscv: Avoid namespace pollutionSebastian Huber2018-06-284-10/+5
* riscv: Optimize and fix interrupt disable/enableSebastian Huber2018-06-281-15/+16
* bsp/riscv: Remove bsp_interrupt_handler_default()Sebastian Huber2018-06-281-9/+0
* bsp/riscv: Rework clock driverSebastian Huber2018-06-284-65/+125
* bsp/riscv: Add device tree support for consoleSebastian Huber2018-06-285-65/+222
* bsp/riscv: Fix vector table for lp64Sebastian Huber2018-06-281-16/+22
* bsp/riscv: Add SMP startup synchronizationSebastian Huber2018-06-281-2/+20
* bsp/riscv: Add device tree supportSebastian Huber2018-06-284-6/+27
* riscv: Add dummy SMP supportSebastian Huber2018-06-285-126/+42
* build: Enable RISC-V SMP buildSebastian Huber2018-06-283-3/+3
* riscv: Implement ISR set/get levelSebastian Huber2018-06-282-9/+18
* bsp/riscv: Load global pointerSebastian Huber2018-06-272-2/+6
* bsp/riscv: Use memset() to clear .bssSebastian Huber2018-06-271-10/+5
* riscv: Format assembler filesSebastian Huber2018-06-275-468/+473
* bsp/riscv: Do not clear integer registers at startSebastian Huber2018-06-271-31/+0
* bsp/riscv: Fix some warningsSebastian Huber2018-06-271-20/+4
* bsp/riscv: Add BSP options to define RAM regionSebastian Huber2018-06-272-3/+25
* bsp/riscv: Remove unused BSP optionsSebastian Huber2018-06-271-10/+0
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