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* rtems: Fix Doxygen commentSebastian Huber2021-07-151-2/+2
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* build: Add the BSP family to the enable setSebastian Huber2021-07-151-1/+6
| | | | | This makes it possible to use the BSP family in expressions of the enabled-by attribute.
* build: Fix formatSebastian Huber2021-07-151-1/+1
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* build: Prefer variant default value over familySebastian Huber2021-07-151-4/+4
| | | | Update #4468.
* build: Fix bsp_defaults commandSebastian Huber2021-07-151-6/+8
| | | | Update #4468.
* build: Add missing default-by-familySebastian Huber2021-07-152-0/+2
| | | | Update #4468.
* spcoverage: Remove test programSebastian Huber2021-07-157-106/+0
| | | | | This program contained an optional test case. It was enabled by the RTEMS_COVERAGE define. The functions under test are not implemented by RTEMS.
* build: Fix the motorola_powerpc default baudrateChris Johns2021-07-151-2/+4
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* build: Use BSP family for optionsChris Johns2021-07-15772-13/+792
| | | | | | | - Optionally add support for 'default-by-family' to allow option to be set by a family and so all related BSPs Close #4468
* bsps/sparc: Improve interrupt affinity supportSebastian Huber2021-07-094-62/+138
| | | | | | | | Fully support the interrupt extension API to set/get the interrupt affinity. Remove LEON3_irq_to_cpu which defined the interrupt to processor mapping in a BSP-specific way. Update #3269.
* bsp/imx: Fix SMP startSebastian Huber2021-07-091-0/+12
| | | | | Flush imx_gic_dist_base so that secondary processors can use the right address.
* bsps/arm: Fix SMP startSebastian Huber2021-07-091-0/+6
| | | | | | | | Skip the data cache initialization if we are a secondary processor. The bug was introduced by e164df5e33608576443b4cd5923a9046358ee773 and did not show up in tests using Qemu since the data cache behaviour is not emulated.
* bsps/imxrt: Fix undefined symbolChristian Mauderer2021-07-081-1/+1
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* bsps/arm: Add start up support for ARMv6 RPi ModelsPranav Dangi2021-07-071-1/+7
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* bsp/raspberrypi: Fix <bsp/irq.h> header guardSebastian Huber2021-07-071-1/+1
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* bsp/imx: Fix pointer from integer warningSebastian Huber2021-07-071-2/+5
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* build: Add option to customize the LINKFLAGSSebastian Huber2021-07-063-1/+19
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* Update test smpstrongapa01Richi Dubey2021-07-061-19/+47
| | | | Update smpstrongapa01 to account for task shifting.
* Fix compiler warnings for schedulerstrongapa.cRichi Dubey2021-07-061-4/+20
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* bsps/imxrt: Simplify linkcmds and make it flexibleChristian Mauderer2021-07-0218-131/+156
| | | | | | | | | Calling the memory FLASH and EXTRAM instead of FLEXSPI and SDRAM makes it simpler to support other types of external RAM. This patch also removes some of the calculations and improves names and documentation to avoid pitfalls. It removes a unnecessary memory definition. Update #4180
* bsps/imxrt: Allow different ARM PLL settingChristian Mauderer2021-07-023-0/+42
| | | | Update #4180
* m68k/uC5282: linkcmds KEEP and SORT sectionsGedare Bloom2021-07-011-15/+19
| | | | | Fixes a problem with bad epilog code in _fini and to keep sections necessary with the -ffunction/data-sections.
* Revert "bsps/zynqmp: Allow any or all CGEMs to be enabled"Kinsey Moore2021-07-015-72/+0
| | | | | | | This reverts commit 10041a4cfc00d5f6876d3d6cfc30c23347b4cf42. This type of configuration does not belong in RTEMS and is better constrained to libbsd where the defines are actually being used.
* bsp/leon3: Move bsp_interrupt_is_valid_vector()Sebastian Huber2021-07-012-16/+14
| | | | | This function is not performance critical. There is no need to implement it inline.
* bsp/leon3: Fix bsp_interrupt_is_valid_vector()Sebastian Huber2021-07-011-3/+7
| | | | | | | | | | The fix to address CID 1399742 (NO_EFFECT) in commit f8b6359415404540864f809cbcffb8c2200261e1 introduced a bug since LEON3_IrqCtrl_EIrq == -1 in case no extended interrupts are supported by the interrupt controller. Fix this by checking for LEON3_IrqCtrl_EIrq > 0. In addition, interrupt number 0 is reserved and should not be used.
* rtems: Do not broadcast to signal a condition varSebastian Huber2021-07-011-1/+1
| | | | Close #4463.
* bsps: Fix GICv3 support for AArch32Sebastian Huber2021-06-301-3/+3
| | | | | | | | | | | The GICv3 support is shared between AArch32 and AArch64. For AArch32, the new AARCH64_IS_NONSECURE is never defined. Use ARM_MULTILIB_ARCH_V4 instead. This issue was introduced by 76c6caad52244ab9a14151620a80ff0f71035b6c. There is still a change in bsp_interrupt_vector_enable() for AArch32 compared to the version before 76c6caad52244ab9a14151620a80ff0f71035b6c.
* bsps/cadence-spi: Fix moduleid offsetKinsey Moore2021-06-291-0/+1
| | | | | Move the moduleid register to the correct offset according to Cadence IP documentation.
* bsps/zynq-uart: Make post baud change kick globalKinsey Moore2021-06-293-5/+14
| | | | | | | | The existing fix for the ZynqMP UART hardware bug only caught the vast majority of instances where it could occur. To fully fix the data corruption, this fix must be applied after every baud rate change. This makes the logic reset and kick apply in any locations where the baud rate could be changed.
* spec/aarch64: fix abi flags for xilinx_versal_ilp32_vck190Gedare Bloom2021-06-291-0/+1
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* arm: For AArch32 use non-shareable memorySebastian Huber2021-06-291-2/+2
| | | | | | | | The Cortex-R52 does not support cache coherency and the shareable memory attribute. If a region is configured to be shareable, then it falls back to use non-cacheable memory. Update #4202.
* arm: Fix AARCH32_PMSA_ATTR_XN valueSebastian Huber2021-06-291-1/+1
| | | | Update #4202.
* arm: Fix AArch32 memory attribute definesSebastian Huber2021-06-291-4/+4
| | | | Update #4202.
* arm: Disable alignment check in PMSA initSebastian Huber2021-06-291-1/+1
| | | | | | | Disable the alignment check through SCTLR[A] in _AArch32_PMSA_Initialize(). Update #4202.
* bsps/zynqmp: Allow any or all CGEMs to be enabledKinsey Moore2021-06-285-0/+72
| | | | | | | Provide the options necessary to enable any combination of CGEM ethernet interfaces in LibBSD. The default is still CGEM3, so this should continue to operate as expected on typical Zynq Ultrascale+ MPSoC development hardware.
* aarch64: whitespace fixes in start.SGedare Bloom2021-06-241-166/+166
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* bsps/aarch64: replace boot options with asm switch codeGedare Bloom2021-06-245-29/+8
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* bsps/aarch64: add non-secure mode and versal supportGedare Bloom2021-06-2411-10/+105
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* bsps/aarch64: add physical secure timerGedare Bloom2021-06-244-0/+42
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* bsps/aarch64: add mnemonic for ICC_IGRPEN1_EL3Gedare Bloom2021-06-241-0/+1
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* bsps/dev/irq: make icspicfgr an indexable arrayGedare Bloom2021-06-241-4/+2
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* aarch64: add support to drop EL3 to EL2Kinsey Moore2021-06-241-1/+26
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* aarch64/xilinx-versal: new BSPs for qemu and vck190Gedare Bloom2021-06-2428-0/+1481
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* Update Strong APA SchedulerRichi Dubey2021-06-243-229/+924
| | | | | | | | | | This change allows for the migration of higher priority tasks on the arrival of a lower priority task limited by affinity constraints. Change license to BSD-2-Clause according to file history and re-licensing agreement. Update #3053.
* sparc: Simplify trap table initializationSebastian Huber2021-06-2415-170/+704
| | | | | | | | | | | | | | | Move _ISR_Handler() to a separate file since it is now only used if a handler is installed by _CPU_ISR_install_raw_handler(). Statically initialize the traps for external interrupts to use the new _SPARC_Interrupt_trap() which directly dispatches the interrupt handlers installed by rtems_interrupt_handler_install() via the BSP-provided _SPARC_Interrupt_dispatch(). Since the trap table is now fully statically initialized, there is no longer a dependency on the Cache Manager in the default configuration. Update #4458.
* bsps: bsp_interrupt_handler_dispatch_unchecked()Sebastian Huber2021-06-241-19/+40
| | | | | | Add bsp_interrupt_handler_dispatch_unchecked() as an alternative to bsp_interrupt_handler_dispatch(). It may be used if the caller can ensure that the vector number is valid.
* sparc: Move FP frame offset defines to cpuimpl.hSebastian Huber2021-06-242-57/+57
| | | | | | This makes them usable in multiple files. Update #4458.
* bsps/sparc: Use rtems_interrupt_handler_install()Sebastian Huber2021-06-2410-31/+98
| | | | | | | Avoid using set_vector() which depends on _ISR_Vector_table(). Prepare for a statically initialized trap table. Update #4458.
* sparc: More reliable bad trap handlingSebastian Huber2021-06-2423-585/+519
| | | | | | | | | | | | | Statically initialize the trap table in start.S to jump to _SPARC_Bad_trap() for all unexpected traps. This enables a proper RTEMS fatal error handling right from the start. Do not rely on the stack and register settings which caused an unexpected trap. Use the ISR stack of the processor to do the fatal error handling. Save the full context which caused the trap. Fatal error handler may use it for error logging. Unify the _CPU_Exception_frame_print() implementations and move it to cpukit. Update #4459.
* sparc: Move ISR handler install routinesSebastian Huber2021-06-244-174/+203
| | | | | | | | Move _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() to separate files. The goal is to make their use optional. Update #4458. Update #4459.
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