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Diffstat (limited to '')
-rw-r--r-- | spec/build/bsps/riscv/riscv/optsifiveuart.yml | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/spec/build/bsps/riscv/riscv/optsifiveuart.yml b/spec/build/bsps/riscv/riscv/optsifiveuart.yml new file mode 100644 index 0000000000..8ff27d0275 --- /dev/null +++ b/spec/build/bsps/riscv/riscv/optsifiveuart.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: + - riscv/kendrytek210 + - riscv/frdme310arty + value: true +- enabled-by: true + value: false +description: | + enables support Sifive UART if defined to a non-zero value, otherwise it is disabled (disabled by default) +enabled-by: true +links: [] +name: RISCV_ENABLE_SIFIVE_UART_SUPPORT +type: build |