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Diffstat (limited to '')
| -rw-r--r-- | spec/build/bsps/powerpc/psim/optclkfastidle.yml | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/spec/build/bsps/powerpc/psim/optclkfastidle.yml b/spec/build/bsps/powerpc/psim/optclkfastidle.yml index df86867fa7..8e96cc9a15 100644 --- a/spec/build/bsps/powerpc/psim/optclkfastidle.yml +++ b/spec/build/bsps/powerpc/psim/optclkfastidle.yml @@ -5,11 +5,11 @@ actions: build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: false -default-by-variant: -- value: true - variants: - - powerpc/psim +default: +- enabled-by: powerpc/psim + value: true +- enabled-by: true + value: false description: | This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing. This can significantly reduce simulation times. enabled-by: true |