diff options
Diffstat (limited to '')
28 files changed, 382 insertions, 36 deletions
diff --git a/spec/build/bsps/microblaze/grp.yml b/spec/build/bsps/microblaze/grp.yml index 3a238f5d6e..9be8ce6172 100644 --- a/spec/build/bsps/microblaze/grp.yml +++ b/spec/build/bsps/microblaze/grp.yml @@ -1,7 +1,10 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause build-type: group +cflags: [] copyrights: - Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +cxxflags: [] enabled-by: true includes: [] install: diff --git a/spec/build/bsps/microblaze/microblaze_fpga/abi.yml b/spec/build/bsps/microblaze/microblaze_fpga/abi.yml index 4665f5d42e..7d78c9842d 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/abi.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/abi.yml @@ -7,11 +7,12 @@ build-type: option copyrights: - Copyright (C) 2021 On-Line Applications Research Corporation (OAR) default: -- -mlittle-endian -- -mno-xl-soft-div -- -mno-xl-soft-mul -- -Wl,-EL -default-by-variant: [] +- enabled-by: true + value: + - -mlittle-endian + - -mno-xl-soft-div + - -mno-xl-soft-mul + - -Wl,-EL description: | ABI flags enabled-by: true diff --git a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml index 0a29e9c200..9ec29f49f6 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml @@ -12,13 +12,11 @@ includes: [] install: [] links: - role: build-dependency - uid: grp -- role: build-dependency - uid: linkcmds -- role: build-dependency uid: tstkcu105_qemu - role: build-dependency uid: ../../opto0 +- role: build-dependency + uid: grp source: - bsps/shared/start/bspreset-loop.c type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml index 9f5d742885..9a1147297a 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml @@ -12,13 +12,11 @@ includes: [] install: [] links: - role: build-dependency - uid: grp -- role: build-dependency - uid: linkcmds -- role: build-dependency uid: tstkcu105_qemu - role: build-dependency uid: ../../opto0 +- role: build-dependency + uid: grp source: - bsps/microblaze/microblaze_fpga/start/bspreset.c type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml index 991ab04a23..aeaa07dc03 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml @@ -1,7 +1,10 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause build-type: group +cflags: [] copyrights: - Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +cxxflags: [] enabled-by: true includes: [] install: [] @@ -18,21 +21,61 @@ links: - role: build-dependency uid: optconsoleinterrupts - role: build-dependency + uid: optdcachebaseaddress +- role: build-dependency + uid: optdcachelinelen +- role: build-dependency + uid: optdcachesize +- role: build-dependency + uid: optdtbheaderpath +- role: build-dependency + uid: opticachebaseaddress +- role: build-dependency + uid: opticachelinelen +- role: build-dependency + uid: opticachesize +- role: build-dependency uid: optintcbaseaddress - role: build-dependency + uid: optmaxuarts +- role: build-dependency + uid: optramlen +- role: build-dependency + uid: optspibaseaddress +- role: build-dependency + uid: optspiirq +- role: build-dependency uid: opttimerbaseaddress - role: build-dependency uid: opttimerfrequency - role: build-dependency uid: optuartlitebaseaddress - role: build-dependency + uid: optuseuart +- role: build-dependency + uid: optuartirq +- role: build-dependency + uid: optuartirq +- role: build-dependency + uid: optconsoleuart +- role: build-dependency + uid: optusefdt +- role: build-dependency uid: ../../obj - role: build-dependency + uid: ../../objdevspixil +- role: build-dependency uid: ../../objirq - role: build-dependency uid: ../../objmem - role: build-dependency + uid: linkcmds +- role: build-dependency uid: ../../bspopts +- role: build-dependency + uid: ../../optfdtuboot +- role: build-dependency + uid: ../../optfdtmxsz type: build use-after: [] use-before: [] diff --git a/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml index d478e86fb6..4f9b310ad3 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml @@ -35,7 +35,7 @@ content: | MEMORY { BRAM (AIW) : ORIGIN = 0x00000000, LENGTH = 0x10000 - RAM : ORIGIN = _TEXT_START_ADDR, LENGTH = 0x1000000 + RAM : ORIGIN = _TEXT_START_ADDR, LENGTH = ${BSP_MICROBLAZE_FPGA_RAM_LENGTH} } REGION_ALIAS ("REGION_START", BRAM); @@ -104,20 +104,20 @@ content: | } > REGION_RODATA AT > REGION_RODATA_LOAD _frodata = . ; - .rodata : { + .rodata : ALIGN_WITH_INPUT { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) CONSTRUCTORS; /* Is this needed? */ } > REGION_RODATA AT > REGION_RODATA_LOAD _erodata = .; - .eh_frame : { - *(.eh_frame) + .eh_frame : ALIGN_WITH_INPUT { + KEEP (*(.eh_frame)) } > REGION_RODATA AT > REGION_RODATA_LOAD .jcr : { *(.jcr) } > REGION_RODATA AT > REGION_RODATA_LOAD - .gcc_except_table : { + .gcc_except_table : ALIGN_WITH_INPUT { *(.gcc_except_table) } > REGION_RODATA AT > REGION_RODATA_LOAD .tdata : ALIGN_WITH_INPUT { diff --git a/spec/build/bsps/microblaze/microblaze_fpga/obj.yml b/spec/build/bsps/microblaze/microblaze_fpga/obj.yml index a211456e1d..52ba596768 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/obj.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/obj.yml @@ -11,10 +11,12 @@ install: - destination: ${BSP_INCLUDEDIR} source: - bsps/microblaze/microblaze_fpga/include/bsp.h - - bsps/microblaze/microblaze_fpga/include/tm27.h - destination: ${BSP_INCLUDEDIR}/bsp source: - bsps/microblaze/microblaze_fpga/include/bsp/irq.h + - bsps/microblaze/microblaze_fpga/include/bsp/jffs2_qspi.h + - bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h + - bsps/microblaze/include/bsp/microblaze-fdt-support.h - bsps/microblaze/include/common/xil_types.h - bsps/microblaze/include/dev/serial/uartlite.h - bsps/microblaze/include/dev/serial/uartlite_l.h @@ -23,21 +25,28 @@ source: - bsps/microblaze/microblaze_fpga/clock/clock.c - bsps/microblaze/microblaze_fpga/console/console-io.c - bsps/microblaze/microblaze_fpga/console/debug-io.c +- bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c +- bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c - bsps/microblaze/microblaze_fpga/irq/irq.c +- bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S - bsps/microblaze/microblaze_fpga/start/_exception_handler.S -- bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S - bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S - bsps/microblaze/microblaze_fpga/start/bspreset.c - bsps/microblaze/microblaze_fpga/start/bspstart.c - bsps/microblaze/microblaze_fpga/start/crtinit.S +- bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S +- bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S +- bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S +- bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S +- bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S - bsps/microblaze/shared/dev/serial/uartlite.c - bsps/microblaze/shared/dev/serial/uartlite_l.c +- bsps/microblaze/shared/fdt/microblaze-fdt-support.c - bsps/shared/cache/nocache.c - bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/cpucounter/cpucounterfrequency.c - bsps/shared/dev/cpucounter/cpucounterread.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/serial/console-termios-init.c - bsps/shared/dev/serial/console-termios.c - bsps/shared/irq/irq-default-handler.c - bsps/shared/start/bspfatal-default.c diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml b/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml index c75a4450e1..61bd7fc48f 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml @@ -5,8 +5,9 @@ actions: build-type: option copyrights: - Copyright (C) 2021 On-Line Applications Research Corporation (OAR) -default: true -default-by-variant: [] +default: +- enabled-by: true + value: true description: | use interrupt driven mode for console enabled-by: true diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml b/spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml new file mode 100644 index 0000000000..c183baed5c --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2023 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 0 +description: | + default uart console device port number +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_CONSOLE_UART +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optdcachebaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optdcachebaseaddress.yml new file mode 100644 index 0000000000..fe828b1cc8 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optdcachebaseaddress.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 0x80000000 +description: | + base address of the data cache +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_DCACHE_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optdcachelinelen.yml b/spec/build/bsps/microblaze/microblaze_fpga/optdcachelinelen.yml new file mode 100644 index 0000000000..0b8ab8bd9b --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optdcachelinelen.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 4 +description: | + length of the data cache line +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optdcachesize.yml b/spec/build/bsps/microblaze/microblaze_fpga/optdcachesize.yml new file mode 100644 index 0000000000..ee7ef4b7ed --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optdcachesize.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 32768 +description: | + size of the data cache in bytes +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_DCACHE_SIZE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optdtbheaderpath.yml b/spec/build/bsps/microblaze/microblaze_fpga/optdtbheaderpath.yml new file mode 100644 index 0000000000..23f8daf4f9 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optdtbheaderpath.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: bsp/microblaze-dtb.h +description: | + the path to the header file containing the device tree binary. See the BSP + documentation for more information. +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opticachebaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/opticachebaseaddress.yml new file mode 100644 index 0000000000..601093f0e0 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/opticachebaseaddress.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 0x80000000 +description: | + base address of the instruction cache +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_ICACHE_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opticachelinelen.yml b/spec/build/bsps/microblaze/microblaze_fpga/opticachelinelen.yml new file mode 100644 index 0000000000..f9671f89ac --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/opticachelinelen.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 8 +description: | + length of the instruction cache line +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opticachesize.yml b/spec/build/bsps/microblaze/microblaze_fpga/opticachesize.yml new file mode 100644 index 0000000000..c8eb421f0b --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/opticachesize.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 32768 +description: | + size of the instruction cache in bytes +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_ICACHE_SIZE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml index 5ed9294ff6..f1c04602bf 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml @@ -7,8 +7,9 @@ actions: build-type: option copyrights: - Copyright (C) 2021 On-Line Applications Research Corporation (OAR) -default: 0x41200000 -default-by-variant: [] +default: +- enabled-by: true + value: 0x41200000 description: | base address of the AXI Interrupt Controller enabled-by: true diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optmaxuarts.yml b/spec/build/bsps/microblaze/microblaze_fpga/optmaxuarts.yml new file mode 100644 index 0000000000..33a0602730 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optmaxuarts.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2023 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 1 +description: | + maximum number of UART devices +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_MAX_UARTS +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optramlen.yml b/spec/build/bsps/microblaze/microblaze_fpga/optramlen.yml new file mode 100644 index 0000000000..43e9142ff8 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optramlen.yml @@ -0,0 +1,23 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2022 On-Line Applications Research (OAR) +default: +- enabled-by: + - microblaze/kcu105 + - microblaze/kcu105_qemu + value: 0x80000000 +- enabled-by: true + value: 0x10000000 +description: | + length of memory area available to the BSP +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_RAM_LENGTH +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optspibaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optspibaseaddress.yml new file mode 100644 index 0000000000..547dbbf9b7 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optspibaseaddress.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2022 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 0x44a00000 +description: | + base address of the AXI Quad SPI +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_SPI_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optspiirq.yml b/spec/build/bsps/microblaze/microblaze_fpga/optspiirq.yml new file mode 100644 index 0000000000..5d26ea6cf5 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optspiirq.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 3 +description: | + IRQ number of the AXI SPI +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_SPI_IRQ_NUM +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml index 93bea74ea3..3e89405d80 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml @@ -7,8 +7,9 @@ actions: build-type: option copyrights: - Copyright (C) 2021 On-Line Applications Research Corporation (OAR) -default: 0x41C00000 -default-by-variant: [] +default: +- enabled-by: true + value: 0x41c00000 description: | base address of the AXI Timer enabled-by: true diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml b/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml index 4734f81bc1..e9cdbb6826 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml @@ -6,8 +6,9 @@ actions: build-type: option copyrights: - Copyright (C) 2021 On-Line Applications Research Corporation (OAR) -default: 100000000 -default-by-variant: [] +default: +- enabled-by: true + value: 100000000 description: | frequency of the AXI Timer enabled-by: true diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml b/spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml new file mode 100644 index 0000000000..3faf6e24e6 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2023 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 3 +description: | + irq number of the AXI UART Lite +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_UART_IRQ +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml index 7dd3123b64..ec15d02709 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml @@ -7,8 +7,9 @@ actions: build-type: option copyrights: - Copyright (C) 2021 On-Line Applications Research Corporation (OAR) -default: 0x40600000 -default-by-variant: [] +default: +- enabled-by: true + value: 0x40600000 description: | base address of the AXI UART Lite enabled-by: true diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optusefdt.yml b/spec/build/bsps/microblaze/microblaze_fpga/optusefdt.yml new file mode 100644 index 0000000000..7e75d59740 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optusefdt.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2022 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: true +description: | + define if FDT is used +enabled-by: true +links: [] +name: BSP_MICROBLAZE_FPGA_USE_FDT +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml b/spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml new file mode 100644 index 0000000000..9136297ba8 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2023 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: true +description: | + define if UART is used +enabled-by: true +links: [] +name: BSP_MICROBLAZE_FPGA_USE_UART +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml index fb9f2bdb00..e906ec46bd 100644 --- a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml +++ b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml @@ -1,14 +1,24 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause actions: - set-test-state: - # expected to fail, don't compile these - minimum: exclude + reason: | + Expected to fail, do not compile these. + state: exclude + tests: + - minimum +- set-test-state: + reason: | + Expected to fail due to GCC issues. + state: expected-fail + tests: + - dl05 build-type: option copyrights: - Copyright (C) 2021 On-Line Applications Research Corporation (OAR) -default: null -default-by-variant: [] +default: [] description: '' enabled-by: true -links: [] +links: +- role: build-dependency + uid: ../../tst-xfail-dl06 type: build |