diff options
Diffstat (limited to '')
29 files changed, 869 insertions, 0 deletions
diff --git a/spec/build/bsps/microblaze/grp.yml b/spec/build/bsps/microblaze/grp.yml new file mode 100644 index 0000000000..9be8ce6172 --- /dev/null +++ b/spec/build/bsps/microblaze/grp.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: group +cflags: [] +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/microblaze/include/bsp/linker-symbols.h +ldflags: [] +links: [] +type: build +use-after: [] +use-before: [] diff --git a/spec/build/bsps/microblaze/microblaze_fpga/abi.yml b/spec/build/bsps/microblaze/microblaze_fpga/abi.yml new file mode 100644 index 0000000000..7d78c9842d --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/abi.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- split: null +- env-append: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: + - -mlittle-endian + - -mno-xl-soft-div + - -mno-xl-soft-mul + - -Wl,-EL +description: | + ABI flags +enabled-by: true +links: [] +name: ABI_FLAGS +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml new file mode 100644 index 0000000000..9ec29f49f6 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml @@ -0,0 +1,22 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: microblaze +bsp: kcu105 +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +enabled-by: true +family: microblaze_fpga +includes: [] +install: [] +links: +- role: build-dependency + uid: tstkcu105_qemu +- role: build-dependency + uid: ../../opto0 +- role: build-dependency + uid: grp +source: +- bsps/shared/start/bspreset-loop.c +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml new file mode 100644 index 0000000000..9a1147297a --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml @@ -0,0 +1,22 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: microblaze +bsp: kcu105_qemu +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +enabled-by: true +family: microblaze_fpga +includes: [] +install: [] +links: +- role: build-dependency + uid: tstkcu105_qemu +- role: build-dependency + uid: ../../opto0 +- role: build-dependency + uid: grp +source: +- bsps/microblaze/microblaze_fpga/start/bspreset.c +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml new file mode 100644 index 0000000000..aeaa07dc03 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml @@ -0,0 +1,81 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: group +cflags: [] +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: [] +ldflags: [] +links: +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: abi +- role: build-dependency + uid: obj +- role: build-dependency + uid: start +- role: build-dependency + uid: optconsoleinterrupts +- role: build-dependency + uid: optdcachebaseaddress +- role: build-dependency + uid: optdcachelinelen +- role: build-dependency + uid: optdcachesize +- role: build-dependency + uid: optdtbheaderpath +- role: build-dependency + uid: opticachebaseaddress +- role: build-dependency + uid: opticachelinelen +- role: build-dependency + uid: opticachesize +- role: build-dependency + uid: optintcbaseaddress +- role: build-dependency + uid: optmaxuarts +- role: build-dependency + uid: optramlen +- role: build-dependency + uid: optspibaseaddress +- role: build-dependency + uid: optspiirq +- role: build-dependency + uid: opttimerbaseaddress +- role: build-dependency + uid: opttimerfrequency +- role: build-dependency + uid: optuartlitebaseaddress +- role: build-dependency + uid: optuseuart +- role: build-dependency + uid: optuartirq +- role: build-dependency + uid: optuartirq +- role: build-dependency + uid: optconsoleuart +- role: build-dependency + uid: optusefdt +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objdevspixil +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: ../../objmem +- role: build-dependency + uid: linkcmds +- role: build-dependency + uid: ../../bspopts +- role: build-dependency + uid: ../../optfdtuboot +- role: build-dependency + uid: ../../optfdtmxsz +type: build +use-after: [] +use-before: [] diff --git a/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml new file mode 100644 index 0000000000..4f9b310ad3 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml @@ -0,0 +1,242 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: config-file +content: | + /* SPDX-License-Identifier: BSD-2-Clause */ + + /* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + ENTRY (_start) + STARTUP (start.o) + _TEXT_START_ADDR = DEFINED(_TEXT_START_ADDR) ? _TEXT_START_ADDR : 0x80000000; + + MEMORY + { + BRAM (AIW) : ORIGIN = 0x00000000, LENGTH = 0x10000 + RAM : ORIGIN = _TEXT_START_ADDR, LENGTH = ${BSP_MICROBLAZE_FPGA_RAM_LENGTH} + } + + REGION_ALIAS ("REGION_START", BRAM); + REGION_ALIAS ("REGION_VECTOR", BRAM); + REGION_ALIAS ("REGION_TEXT", RAM); + REGION_ALIAS ("REGION_TEXT_LOAD", RAM); + REGION_ALIAS ("REGION_RODATA", RAM); + REGION_ALIAS ("REGION_RODATA_LOAD", RAM); + REGION_ALIAS ("REGION_DATA", RAM); + REGION_ALIAS ("REGION_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_FAST_DATA", RAM); + REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_BSS", RAM); + REGION_ALIAS ("REGION_WORK", RAM); + REGION_ALIAS ("REGION_STACK", RAM); + + SECTIONS + { + .vectors.reset 0x0 : { KEEP (*(.vectors.reset)) } = 0 + .vectors.sw_exception 0x8 : { KEEP (*(.vectors.sw_exception)) } = 0 + .vectors.interrupt 0x10 : { KEEP (*(.vectors.interrupt)) } = 0 + .vectors.debug_sw_break 0x18 : { KEEP (*(.vectors.debug_sw_break)) } = 0 + .vectors.hw_exception 0x20 : { KEEP (*(.vectors.hw_exception)) } = 0 + . = _TEXT_START_ADDR; + .text : ALIGN_WITH_INPUT { + bsp_section_text_begin = .; + *(.text.unlikely .text.*_unlikely) + *(.text .stub .text.* .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .init : ALIGN_WITH_INPUT { + KEEP (*(.init)) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .fini : ALIGN_WITH_INPUT { + KEEP (*(.fini)) + + /* + * If requested, align the size of the combined start and text + * section to the next power of two to meet MPU region + * alignment requirements. + */ + . = DEFINED (bsp_align_text_and_rodata_end_to_power_of_2) ? + bsp_section_start_begin + + ALIGN (. - bsp_section_start_begin, + 1 << LOG2CEIL (. - bsp_section_start_begin)) : .; + + bsp_section_text_end = .; + } > REGION_TEXT AT > REGION_TEXT_LOAD + bsp_section_text_size = bsp_section_text_end - bsp_section_text_begin; + bsp_section_text_load_begin = LOADADDR (.text); + bsp_section_text_load_end = bsp_section_text_load_begin + bsp_section_text_size; + + . = ALIGN(4); + + /* Added to handle pic code */ + .got : { + *(.got) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .got1 : { + *(.got1) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .got2 : { + *(.got2) + } > REGION_RODATA AT > REGION_RODATA_LOAD + + _frodata = . ; + .rodata : ALIGN_WITH_INPUT { + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + CONSTRUCTORS; /* Is this needed? */ + } > REGION_RODATA AT > REGION_RODATA_LOAD + _erodata = .; + .eh_frame : ALIGN_WITH_INPUT { + KEEP (*(.eh_frame)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .jcr : { + *(.jcr) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gcc_except_table : ALIGN_WITH_INPUT { + *(.gcc_except_table) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tdata : ALIGN_WITH_INPUT { + _TLS_Data_begin = .; + *(.tdata .tdata.* .gnu.linkonce.td.*) + _TLS_Data_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tbss : ALIGN_WITH_INPUT { + _TLS_BSS_begin = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) + _TLS_BSS_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; + _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; + _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; + _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; + _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; + _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); + + .ctors : { + _dummy_symbol__ = .; + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors*)) + __CTOR_END__ = .; + ___CTORS_END___ = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + PROVIDE(__DTOR_END__ = .); + PROVIDE(___DTORS_END___ = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rtemsroset : { + /* Special FreeBSD linker set sections */ + __start_set_sysctl_set = .; + *(set_sysctl_*); + __stop_set_sysctl_set = .; + *(set_domain_*); + *(set_pseudo_*); + + KEEP (*(SORT(.rtemsroset.*))) + bsp_section_rodata_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + + .data : ALIGN_WITH_INPUT { + bsp_section_data_begin = .; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } > REGION_DATA AT > REGION_DATA_LOAD + .data1 : ALIGN_WITH_INPUT { + *(.data1) + } > REGION_DATA AT > REGION_DATA_LOAD + .rtemsrwset : ALIGN_WITH_INPUT { + KEEP (*(SORT(.rtemsrwset.*))) + bsp_section_data_end = .; + } > REGION_DATA AT > REGION_DATA_LOAD + bsp_section_data_size = bsp_section_data_end - bsp_section_data_begin; + bsp_section_data_load_begin = LOADADDR (.data); + bsp_section_data_load_end = bsp_section_data_load_begin + bsp_section_data_size; + + .bss : ALIGN_WITH_INPUT { + bsp_section_bss_begin = .; + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + bsp_section_bss_end = .; + } > REGION_BSS AT > REGION_BSS + bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_begin; + + . = ALIGN(8); + + .rtemsstack (NOLOAD) : ALIGN_WITH_INPUT { + bsp_section_rtemsstack_begin = .; + *(SORT_BY_ALIGNMENT (SORT_BY_NAME (.rtemsstack*))) + bsp_section_rtemsstack_end = .; + } > REGION_WORK AT > REGION_WORK + bsp_section_rtemsstack_size = bsp_section_rtemsstack_end - bsp_section_rtemsstack_begin; + + .work : ALIGN_WITH_INPUT { + /* + * The work section will occupy the remaining REGION_WORK region and + * contains the RTEMS work space and heap. + */ + bsp_section_work_begin = .; + . += ORIGIN (REGION_WORK) + LENGTH (REGION_WORK) - ABSOLUTE (.); + bsp_section_work_end = .; + } > REGION_WORK AT > REGION_WORK + bsp_section_work_size = bsp_section_work_end - bsp_section_work_begin; + + .stack : ALIGN_WITH_INPUT { + /* + * The stack section will occupy the remaining REGION_STACK region and may + * contain the task stacks. Depending on the region distribution this + * section may be of zero size. + */ + bsp_section_stack_begin = .; + . += ORIGIN (REGION_STACK) + LENGTH (REGION_STACK) - ABSOLUTE (.); + bsp_section_stack_end = .; + } > REGION_STACK AT > REGION_STACK + bsp_section_stack_size = bsp_section_stack_end - bsp_section_stack_begin; + + RamBase = ORIGIN (REGION_WORK); + RamSize = LENGTH (REGION_WORK); + RamEnd = RamBase + RamSize; + WorkAreaBase = bsp_section_work_begin; + HeapSize = 0; + } +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/obj.yml b/spec/build/bsps/microblaze/microblaze_fpga/obj.yml new file mode 100644 index 0000000000..52ba596768 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/obj.yml @@ -0,0 +1,55 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/microblaze/microblaze_fpga/include/bsp.h +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/microblaze/microblaze_fpga/include/bsp/irq.h + - bsps/microblaze/microblaze_fpga/include/bsp/jffs2_qspi.h + - bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h + - bsps/microblaze/include/bsp/microblaze-fdt-support.h + - bsps/microblaze/include/common/xil_types.h + - bsps/microblaze/include/dev/serial/uartlite.h + - bsps/microblaze/include/dev/serial/uartlite_l.h +links: [] +source: +- bsps/microblaze/microblaze_fpga/clock/clock.c +- bsps/microblaze/microblaze_fpga/console/console-io.c +- bsps/microblaze/microblaze_fpga/console/debug-io.c +- bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c +- bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c +- bsps/microblaze/microblaze_fpga/irq/irq.c +- bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S +- bsps/microblaze/microblaze_fpga/start/_exception_handler.S +- bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S +- bsps/microblaze/microblaze_fpga/start/bspreset.c +- bsps/microblaze/microblaze_fpga/start/bspstart.c +- bsps/microblaze/microblaze_fpga/start/crtinit.S +- bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S +- bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S +- bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S +- bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S +- bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S +- bsps/microblaze/shared/dev/serial/uartlite.c +- bsps/microblaze/shared/dev/serial/uartlite_l.c +- bsps/microblaze/shared/fdt/microblaze-fdt-support.c +- bsps/shared/cache/nocache.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/dev/cpucounter/cpucounterfrequency.c +- bsps/shared/dev/cpucounter/cpucounterread.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/irq/irq-default-handler.c +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/gettargethash-default.c +- bsps/shared/start/sbrk.c +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml b/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml new file mode 100644 index 0000000000..61bd7fc48f --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: true +description: | + use interrupt driven mode for console +enabled-by: true +links: [] +name: BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml b/spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml new file mode 100644 index 0000000000..c183baed5c --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2023 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 0 +description: | + default uart console device port number +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_CONSOLE_UART +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optdcachebaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optdcachebaseaddress.yml new file mode 100644 index 0000000000..fe828b1cc8 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optdcachebaseaddress.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 0x80000000 +description: | + base address of the data cache +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_DCACHE_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optdcachelinelen.yml b/spec/build/bsps/microblaze/microblaze_fpga/optdcachelinelen.yml new file mode 100644 index 0000000000..0b8ab8bd9b --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optdcachelinelen.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 4 +description: | + length of the data cache line +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optdcachesize.yml b/spec/build/bsps/microblaze/microblaze_fpga/optdcachesize.yml new file mode 100644 index 0000000000..ee7ef4b7ed --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optdcachesize.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 32768 +description: | + size of the data cache in bytes +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_DCACHE_SIZE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optdtbheaderpath.yml b/spec/build/bsps/microblaze/microblaze_fpga/optdtbheaderpath.yml new file mode 100644 index 0000000000..23f8daf4f9 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optdtbheaderpath.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: bsp/microblaze-dtb.h +description: | + the path to the header file containing the device tree binary. See the BSP + documentation for more information. +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opticachebaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/opticachebaseaddress.yml new file mode 100644 index 0000000000..601093f0e0 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/opticachebaseaddress.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 0x80000000 +description: | + base address of the instruction cache +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_ICACHE_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opticachelinelen.yml b/spec/build/bsps/microblaze/microblaze_fpga/opticachelinelen.yml new file mode 100644 index 0000000000..f9671f89ac --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/opticachelinelen.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 8 +description: | + length of the instruction cache line +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opticachesize.yml b/spec/build/bsps/microblaze/microblaze_fpga/opticachesize.yml new file mode 100644 index 0000000000..c8eb421f0b --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/opticachesize.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 32768 +description: | + size of the instruction cache in bytes +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_ICACHE_SIZE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml new file mode 100644 index 0000000000..f1c04602bf --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 0x41200000 +description: | + base address of the AXI Interrupt Controller +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_INTC_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optmaxuarts.yml b/spec/build/bsps/microblaze/microblaze_fpga/optmaxuarts.yml new file mode 100644 index 0000000000..33a0602730 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optmaxuarts.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2023 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 1 +description: | + maximum number of UART devices +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_MAX_UARTS +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optramlen.yml b/spec/build/bsps/microblaze/microblaze_fpga/optramlen.yml new file mode 100644 index 0000000000..43e9142ff8 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optramlen.yml @@ -0,0 +1,23 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2022 On-Line Applications Research (OAR) +default: +- enabled-by: + - microblaze/kcu105 + - microblaze/kcu105_qemu + value: 0x80000000 +- enabled-by: true + value: 0x10000000 +description: | + length of memory area available to the BSP +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_RAM_LENGTH +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optspibaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optspibaseaddress.yml new file mode 100644 index 0000000000..547dbbf9b7 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optspibaseaddress.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2022 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 0x44a00000 +description: | + base address of the AXI Quad SPI +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_SPI_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optspiirq.yml b/spec/build/bsps/microblaze/microblaze_fpga/optspiirq.yml new file mode 100644 index 0000000000..5d26ea6cf5 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optspiirq.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 3 +description: | + IRQ number of the AXI SPI +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_SPI_IRQ_NUM +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml new file mode 100644 index 0000000000..3e89405d80 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 0x41c00000 +description: | + base address of the AXI Timer +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_TIMER_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml b/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml new file mode 100644 index 0000000000..e9cdbb6826 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 100000000 +description: | + frequency of the AXI Timer +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_TIMER_FREQUENCY +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml b/spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml new file mode 100644 index 0000000000..3faf6e24e6 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2023 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 3 +description: | + irq number of the AXI UART Lite +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_UART_IRQ +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml new file mode 100644 index 0000000000..ec15d02709 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: 0x40600000 +description: | + base address of the AXI UART Lite +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_UART_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optusefdt.yml b/spec/build/bsps/microblaze/microblaze_fpga/optusefdt.yml new file mode 100644 index 0000000000..7e75d59740 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optusefdt.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2022 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: true +description: | + define if FDT is used +enabled-by: true +links: [] +name: BSP_MICROBLAZE_FPGA_USE_FDT +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml b/spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml new file mode 100644 index 0000000000..9136297ba8 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2023 On-Line Applications Research Corporation (OAR) +default: +- enabled-by: true + value: true +description: | + define if UART is used +enabled-by: true +links: [] +name: BSP_MICROBLAZE_FPGA_USE_UART +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/start.yml b/spec/build/bsps/microblaze/microblaze_fpga/start.yml new file mode 100644 index 0000000000..38de263733 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/start.yml @@ -0,0 +1,14 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +asflags: [] +build-type: start-file +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +enabled-by: true +includes: [] +install-path: ${BSP_LIBDIR} +links: [] +source: +- bsps/microblaze/shared/start/start.S +target: start.o +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml new file mode 100644 index 0000000000..e906ec46bd --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml @@ -0,0 +1,24 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- set-test-state: + reason: | + Expected to fail, do not compile these. + state: exclude + tests: + - minimum +- set-test-state: + reason: | + Expected to fail due to GCC issues. + state: expected-fail + tests: + - dl05 +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: [] +description: '' +enabled-by: true +links: +- role: build-dependency + uid: ../../tst-xfail-dl06 +type: build |