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-rw-r--r--spec/build/bsps/dev/irq/objarmgicv3.yml31
-rw-r--r--spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml30
-rw-r--r--spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml19
-rw-r--r--spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml19
-rw-r--r--spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml30
-rw-r--r--spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml19
-rw-r--r--spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml19
-rw-r--r--spec/build/bsps/dev/irq/optarmgic-icc-sre.yml19
8 files changed, 186 insertions, 0 deletions
diff --git a/spec/build/bsps/dev/irq/objarmgicv3.yml b/spec/build/bsps/dev/irq/objarmgicv3.yml
new file mode 100644
index 0000000000..382d767dd7
--- /dev/null
+++ b/spec/build/bsps/dev/irq/objarmgicv3.yml
@@ -0,0 +1,31 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH & Co. KG
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/dev/irq
+ source:
+ - bsps/include/dev/irq/arm-gicv3.h
+links:
+- role: build-dependency
+ uid: optarmgic-icc-bpr0
+- role: build-dependency
+ uid: optarmgic-icc-bpr1
+- role: build-dependency
+ uid: optarmgic-icc-ctrl
+- role: build-dependency
+ uid: optarmgic-icc-igrpen0
+- role: build-dependency
+ uid: optarmgic-icc-igrpen1
+- role: build-dependency
+ uid: optarmgic-icc-pmr
+- role: build-dependency
+ uid: optarmgic-icc-sre
+source:
+- bsps/shared/dev/irq/arm-gicv3.c
+type: build
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml b/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml
new file mode 100644
index 0000000000..44d2671eb6
--- /dev/null
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml
@@ -0,0 +1,30 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH & Co. KG
+default:
+- enabled-by:
+ - aarch64/a53_ilp32_qemu
+ - aarch64/a53_lp64_qemu
+ - aarch64/a72_ilp32_qemu
+ - aarch64/a72_lp64_qemu
+ - aarch64/raspberrypi4b
+ - aarch64/xilinx_versal_aiedge
+ - aarch64/xilinx_versal_qemu
+ - aarch64/xilinx_versal_vck190
+ - bsps/aarch64/xilinx-zynqmp
+ value: null
+- enabled-by: true
+ value: 0x00000002
+description: |
+ Defines the initial value of the ICC_BPR0 register of the ARM GIC CPU
+ Interface. The value is optional. If it is not defined, then the register
+ is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_BPR0
+type: build
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml b/spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml
new file mode 100644
index 0000000000..23dfb8239d
--- /dev/null
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 0x00000003
+description: |
+ Defines the initial value of the ICC_BPR1 register of the ARM GIC CPU
+ Interface. The value is optional. If it is not defined, then the register
+ is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_BPR1
+type: build
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml b/spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml
new file mode 100644
index 0000000000..87d160c705
--- /dev/null
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 0x00000000
+description: |
+ Defines the initial value of the ICC_CTRL register of the ARM GIC CPU
+ Interface. The value is optional. If it is not defined, then the register
+ is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_CTRL
+type: build
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml
new file mode 100644
index 0000000000..9b552c3f96
--- /dev/null
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml
@@ -0,0 +1,30 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH & Co. KG
+default:
+- enabled-by:
+ - aarch64/a53_ilp32_qemu
+ - aarch64/a53_lp64_qemu
+ - aarch64/a72_ilp32_qemu
+ - aarch64/a72_lp64_qemu
+ - aarch64/raspberrypi4b
+ - aarch64/xilinx_versal_aiedge
+ - aarch64/xilinx_versal_qemu
+ - aarch64/xilinx_versal_vck190
+ - bsps/aarch64/xilinx-zynqmp
+ value: null
+- enabled-by: true
+ value: 0x00000001
+description: |
+ Defines the initial value of the ICC_IGRPEN0 register of the ARM GIC CPU
+ Interface. The value is optional. If it is not defined, then the register
+ is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_IGRPEN0
+type: build
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml
new file mode 100644
index 0000000000..023505fce0
--- /dev/null
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 0x00000001
+description: |
+ Defines the initial value of the ICC_IGRPEN1 register of the ARM GIC CPU
+ Interface. The value is optional. If it is not defined, then the register
+ is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_IGRPEN1
+type: build
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml b/spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml
new file mode 100644
index 0000000000..6f742b0825
--- /dev/null
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 0x000000ff
+description: |
+ Defines the initial value of the ICC_PMR register of the ARM GIC CPU
+ Interface. The value is optional. If it is not defined, then the register
+ is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_PMR
+type: build
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-sre.yml b/spec/build/bsps/dev/irq/optarmgic-icc-sre.yml
new file mode 100644
index 0000000000..ff6283b2d4
--- /dev/null
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-sre.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 0x00000003
+description: |
+ Defines the initial value of the ICC_SRE register of the ARM GIC CPU
+ Interface. The value is optional. If it is not defined, then the register
+ is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_SRE
+type: build
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-27 18:20:07 +0000