diff options
Diffstat (limited to '')
35 files changed, 516 insertions, 69 deletions
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml new file mode 100644 index 0000000000..06795eb416 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- split: null +- env-append: null +build-type: option +copyrights: +- Copyright (C) 2023 Reflex Aerospace GmbH +default: +- enabled-by: true + value: + - -march=armv7-r + - -mthumb + - -mfpu=vfpv3-d16 + - -mfloat-abi=hard +description: | + ABI flags +enabled-by: true +links: [] +name: ABI_FLAGS +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml new file mode 100644 index 0000000000..f6c228c79d --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: arm +bsp: xilinx_zynqmp_mercuryxu5_rpu +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2023 Reflex Aerospace GmbH +cppflags: [] +enabled-by: true +family: xilinx-zynqmp-rpu +includes: [] +install: [] +links: +- role: build-dependency + uid: grp +source: [] +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bsprpu.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bsprpu.yml new file mode 100644 index 0000000000..d4073d8248 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bsprpu.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: arm +bsp: xilinx_zynqmp_rpu +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2024 embedded brains GmbH +cppflags: [] +enabled-by: true +family: xilinx-zynqmp-rpu +includes: [] +install: [] +links: +- role: build-dependency + uid: grp +source: [] +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml new file mode 100644 index 0000000000..a088c69052 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml @@ -0,0 +1,73 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: group +cflags: [] +copyrights: +- Copyright (C) 2023 Reflex Aerospace GmbH +cppflags: [] +cxxflags: [] +enabled-by: true +includes: +- bsps/include/xil +- bsps/include/xil/${XIL_SUPPORT_PATH} +install: [] +ldflags: [] +links: +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: abi +- role: build-dependency + uid: optclkfastidle +- role: build-dependency + uid: optclkuart +- role: build-dependency + uid: optconirq +- role: build-dependency + uid: ../../optxilclockttcbaseaddr +- role: build-dependency + uid: ../../optxilclockttcirq +- role: build-dependency + uid: ../../optxilclockttcrefclk +- role: build-dependency + uid: optint0len +- role: build-dependency + uid: optint0ori +- role: build-dependency + uid: optint1len +- role: build-dependency + uid: optint1ori +- role: build-dependency + uid: optramlen +- role: build-dependency + uid: optramori +- role: build-dependency + uid: optresetvec +- role: build-dependency + uid: optnocachelen +- role: build-dependency + uid: obj +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: ../../objdevserialzynq +- role: build-dependency + uid: ../../objdevspizynq +- role: build-dependency + uid: ../../objdevspixil +- role: build-dependency + uid: ../../objmem +- role: build-dependency + uid: ../../opto0 +- role: build-dependency + uid: linkcmds +- role: build-dependency + uid: ../../bspopts +- role: build-dependency + uid: ../../objxilinxsupport +type: build +use-after: [] +use-before: [] diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml new file mode 100644 index 0000000000..9c8a6d1cd6 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml @@ -0,0 +1,46 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: config-file +content: | + MEMORY { + RAM_INT_0 : ORIGIN = ${ZYNQMP_RPU_RAM_INT_0_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_INT_0_LENGTH:#010x} + RAM_INT_1 : ORIGIN = ${ZYNQMP_RPU_RAM_INT_1_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_INT_1_LENGTH:#010x} + RAM : ORIGIN = ${ZYNQMP_RPU_RAM_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_LENGTH:#010x} - ${ZYNQMP_RPU_RAM_ORIGIN:#010x} - ${ZYNQMP_RPU_RAM_NOCACHE_LENGTH:#010x} + NOCACHE : ORIGIN = ${ZYNQMP_RPU_RAM_LENGTH:#010x} - ${ZYNQMP_RPU_RAM_NOCACHE_LENGTH:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_NOCACHE_LENGTH:#010x} + } + + REGION_ALIAS ("REGION_START", RAM_INT_0); + REGION_ALIAS ("REGION_VECTOR", RAM_INT_0); + REGION_ALIAS ("REGION_TEXT", RAM); + REGION_ALIAS ("REGION_TEXT_LOAD", RAM); + REGION_ALIAS ("REGION_RODATA", RAM); + REGION_ALIAS ("REGION_RODATA_LOAD", RAM); + REGION_ALIAS ("REGION_DATA", RAM); + REGION_ALIAS ("REGION_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_FAST_TEXT", RAM); + REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM); + REGION_ALIAS ("REGION_FAST_DATA", RAM); + REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_BSS", RAM); + REGION_ALIAS ("REGION_WORK", RAM); + REGION_ALIAS ("REGION_STACK", RAM); + REGION_ALIAS ("REGION_NOCACHE", NOCACHE); + REGION_ALIAS ("REGION_NOCACHE_LOAD", NOCACHE); + + bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024; + + bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M; + + bsp_vector_table_in_start_section = 1; + + INCLUDE linkcmds.armv4 + + # define symbols needed by the R5 xil_cache.c + _stack_end = bsp_section_stack_end; + __undef_stack = bsp_section_stack_begin; +copyrights: +- Copyright (C) 2023 Reflex Aerospace GmbH +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/obj.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/obj.yml new file mode 100644 index 0000000000..4fb536c96a --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/obj.yml @@ -0,0 +1,42 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2023 Reflex Aerospace GmbH +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/arm/xilinx-zynqmp-rpu/include/bsp.h +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h +- destination: ${BSP_INCLUDEDIR}/peripheral_maps + source: + - bsps/include/peripheral_maps/xilinx_zynqmp.h +links: [] +source: +- bsps/shared/cache/nocache.c +- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c +- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c +- bsps/arm/shared/start/bsp-start-memcpy.S +- bsps/arm/xilinx-zynqmp-rpu/console/console-config.c +- bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c +- bsps/arm/xilinx-zynqmp-rpu/start/bspstart.c +- bsps/arm/xilinx-zynqmp-rpu/start/bspstarthooks.c +- bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c +- bsps/shared/dev/clock/xil-ttc.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/irq/arm-gicv2.c +- bsps/shared/dev/irq/arm-gicv2-zynqmp.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/irq/irq-default-handler.c +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/gettargethash-default.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkfastidle.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkfastidle.yml new file mode 100644 index 0000000000..f0b83e1402 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkfastidle.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: + - arm/lm3s6965_qemu + - arm/realview_pbx_a9_qemu + - arm/xilinx_zynq_a9_qemu + value: true +- enabled-by: true + value: false +description: | + This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing. This can significantly reduce simulation times. +enabled-by: true +links: [] +name: CLOCK_DRIVER_USE_FAST_IDLE +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml new file mode 100644 index 0000000000..4ee4e63dbb --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 100000000 +description: | + Zynq UART clock frequency in Hz +enabled-by: true +format: '{}' +links: [] +name: ZYNQ_CLOCK_UART +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optconirq.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optconirq.yml new file mode 100644 index 0000000000..e9bc6bedc6 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optconirq.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: true +description: | + use interrupt driven mode for console devices (used by default) +enabled-by: true +links: [] +name: ZYNQ_CONSOLE_USE_INTERRUPTS +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml new file mode 100644 index 0000000000..0799dd6205 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00010000 +description: '' +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQMP_RPU_RAM_INT_0_LENGTH +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml new file mode 100644 index 0000000000..34c42efe17 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00000000 +description: '' +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQMP_RPU_RAM_INT_0_ORIGIN +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1len.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1len.yml new file mode 100644 index 0000000000..667c38549e --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1len.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00010000 +description: '' +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQMP_RPU_RAM_INT_1_LENGTH +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml new file mode 100644 index 0000000000..0a1fd3e989 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00020000 +description: '' +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQMP_RPU_RAM_INT_1_ORIGIN +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optnocachelen.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optnocachelen.yml new file mode 100644 index 0000000000..349190fe43 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optnocachelen.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00100000 +description: | + length of nocache RAM region +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQMP_RPU_RAM_NOCACHE_LENGTH +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml new file mode 100644 index 0000000000..d684f5a06d --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2023 Reflex Aerospace GmbH +default: +- enabled-by: true + value: true +description: | + Sets the target processing unit to the RPU (R5F) cores. +enabled-by: true +format: '{}' +links: [] +name: ZYNQMP_PROC_UNIT_RPU +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramlen.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramlen.yml new file mode 100644 index 0000000000..b7d84b933e --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramlen.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x10000000 +description: | + override a BSP's default RAM length +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQMP_RPU_RAM_LENGTH +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml new file mode 100644 index 0000000000..d5b163781a --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00100000 +description: '' +enabled-by: true +format: '{:#010x}' +links: [] +name: ZYNQMP_RPU_RAM_ORIGIN +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optresetvec.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optresetvec.yml new file mode 100644 index 0000000000..206a6f2801 --- /dev/null +++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optresetvec.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: false +description: | + reset vector address for BSP start +enabled-by: true +links: [] +name: BSP_START_RESET_VECTOR +type: build diff --git a/spec/build/bsps/arm/xilinx-zynqmp/abi.yml b/spec/build/bsps/arm/xilinx-zynqmp/abi.yml index 23c66bb5b8..3945b46365 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/abi.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/abi.yml @@ -5,14 +5,15 @@ actions: - env-append: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG default: -- -march=armv7-a -- -mthumb -- -mfpu=neon -- -mfloat-abi=hard -- -mtune=cortex-a53 -default-by-variant: [] +- enabled-by: true + value: + - -march=armv7-a + - -mthumb + - -mfpu=neon + - -mfloat-abi=hard + - -mtune=cortex-a53 description: | ABI flags enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml index 0d336cc6cf..d947123247 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml @@ -4,7 +4,7 @@ bsp: xilinx_zynqmp_ultra96 build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: xilinx-zynqmp @@ -13,7 +13,6 @@ install: - destination: ${BSP_INCLUDEDIR} source: - bsps/arm/xilinx-zynqmp/include/bsp.h - - bsps/arm/xilinx-zynqmp/include/tm27.h - destination: ${BSP_INCLUDEDIR}/bsp source: - bsps/arm/xilinx-zynqmp/include/bsp/irq.h @@ -44,8 +43,6 @@ links: - role: build-dependency uid: optconirq - role: build-dependency - uid: ../../optconminor -- role: build-dependency uid: optint0len - role: build-dependency uid: optint0ori @@ -74,6 +71,8 @@ links: - role: build-dependency uid: ../../objdevspixil - role: build-dependency + uid: ../../objmem +- role: build-dependency uid: ../../opto2 - role: build-dependency uid: linkcmds @@ -81,16 +80,18 @@ links: uid: ../../bspopts source: - bsps/arm/shared/cache/cache-cp15.c +- bsps/arm/shared/cache/cache-v7ar-disable-data.S - bsps/arm/shared/clock/arm-generic-timer-aarch32.c - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c - bsps/arm/shared/start/bsp-start-memcpy.S +- bsps/arm/shared/start/bspstarthook0-empty.c - bsps/arm/xilinx-zynqmp/console/console-config.c - bsps/arm/xilinx-zynqmp/start/bspreset.c - bsps/arm/xilinx-zynqmp/start/bspstart.c - bsps/arm/xilinx-zynqmp/start/bspstarthooks.c - bsps/arm/xilinx-zynqmp/start/bspstartmmu.c -- bsps/shared/dev/btimer/btimer-stub.c +- bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/clock/arm-generic-timer.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c - bsps/shared/dev/irq/arm-gicv2.c @@ -98,7 +99,6 @@ source: - bsps/shared/dev/serial/console-termios.c - bsps/shared/irq/irq-default-handler.c - bsps/shared/start/bspfatal-default.c -- bsps/shared/start/bspgetworkarea-default.c - bsps/shared/start/gettargethash-default.c - bsps/shared/start/sbrk.c - bsps/shared/start/stackalloc.c diff --git a/spec/build/bsps/arm/xilinx-zynqmp/linkcmds.yml b/spec/build/bsps/arm/xilinx-zynqmp/linkcmds.yml index 77bd5fb763..f23369b1de 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/linkcmds.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/linkcmds.yml @@ -38,7 +38,7 @@ content: | INCLUDE linkcmds.armv4 copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG enabled-by: true install-path: ${BSP_LIBDIR} links: [] diff --git a/spec/build/bsps/arm/xilinx-zynqmp/objsmp.yml b/spec/build/bsps/arm/xilinx-zynqmp/objsmp.yml index e8b954b5cb..8ae414e9b6 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/objsmp.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/objsmp.yml @@ -2,7 +2,7 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause build-type: objects cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] cxxflags: [] enabled-by: diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optcachedata.yml b/spec/build/bsps/arm/xilinx-zynqmp/optcachedata.yml index 1664b0fc31..01b4959995 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optcachedata.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optcachedata.yml @@ -4,12 +4,15 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-variant: -- value: false - variants: - - arm/.*qemu +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: + - arm/lm3s6965_qemu + - arm/realview_pbx_a9_qemu + - arm/xilinx_zynq_a9_qemu + value: false +- enabled-by: true + value: true description: | enable data cache enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optcacheinst.yml b/spec/build/bsps/arm/xilinx-zynqmp/optcacheinst.yml index b191133af9..62607fb235 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optcacheinst.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optcacheinst.yml @@ -4,12 +4,15 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-variant: -- value: false - variants: - - arm/.*qemu +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: + - arm/lm3s6965_qemu + - arm/realview_pbx_a9_qemu + - arm/xilinx_zynq_a9_qemu + value: false +- enabled-by: true + value: true description: | enable instruction cache enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optclkfastidle.yml b/spec/build/bsps/arm/xilinx-zynqmp/optclkfastidle.yml index b800b20428..f0b83e1402 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optclkfastidle.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optclkfastidle.yml @@ -4,12 +4,15 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: false -default-by-variant: -- value: true - variants: - - arm/.*qemu +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: + - arm/lm3s6965_qemu + - arm/realview_pbx_a9_qemu + - arm/xilinx_zynq_a9_qemu + value: true +- enabled-by: true + value: false description: | This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing. This can significantly reduce simulation times. enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optclkuart.yml b/spec/build/bsps/arm/xilinx-zynqmp/optclkuart.yml index a2def36606..4ee4e63dbb 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optclkuart.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optclkuart.yml @@ -4,12 +4,10 @@ actions: - define: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 100000000 -default-by-variant: -- value: 100000000 - variants: - - arm/xilinx_zynqmp_ultra96.* +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 100000000 description: | Zynq UART clock frequency in Hz enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optconirq.yml b/spec/build/bsps/arm/xilinx-zynqmp/optconirq.yml index ecb91d81a3..e9bc6bedc6 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optconirq.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optconirq.yml @@ -4,9 +4,10 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: true description: | use interrupt driven mode for console devices (used by default) enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optint0len.yml b/spec/build/bsps/arm/xilinx-zynqmp/optint0len.yml index 55b3487553..dacb8d2541 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optint0len.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optint0len.yml @@ -6,9 +6,10 @@ actions: - format-and-define: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 196608 -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00030000 description: '' enabled-by: true format: '{:#010x}' diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optint0ori.yml b/spec/build/bsps/arm/xilinx-zynqmp/optint0ori.yml index f6a8b5f7d4..8f83ceeb07 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optint0ori.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optint0ori.yml @@ -6,9 +6,10 @@ actions: - format-and-define: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 0 -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00000000 description: '' enabled-by: true format: '{:#010x}' diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optint1len.yml b/spec/build/bsps/arm/xilinx-zynqmp/optint1len.yml index bdaef49951..6d0576bb24 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optint1len.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optint1len.yml @@ -6,9 +6,10 @@ actions: - format-and-define: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 65024 -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x0000fe00 description: '' enabled-by: true format: '{:#010x}' diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optint1ori.yml b/spec/build/bsps/arm/xilinx-zynqmp/optint1ori.yml index 55caa6f4a2..04c44dedff 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optint1ori.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optint1ori.yml @@ -6,9 +6,10 @@ actions: - format-and-define: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 4294901760 -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0xffff0000 description: '' enabled-by: true format: '{:#010x}' diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optnocachelen.yml b/spec/build/bsps/arm/xilinx-zynqmp/optnocachelen.yml index 4b9118d926..b82dfa7410 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optnocachelen.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optnocachelen.yml @@ -6,9 +6,10 @@ actions: - format-and-define: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 1048576 -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00100000 description: | length of nocache RAM region enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optramlen.yml b/spec/build/bsps/arm/xilinx-zynqmp/optramlen.yml index 6efaf7b13b..1cdb31d4d7 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optramlen.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optramlen.yml @@ -6,12 +6,12 @@ actions: - format-and-define: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 268435456 -default-by-variant: -- value: 2147483648 - variants: - - arm/xilinx_zynqmp_ultra96 +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: arm/xilinx_zynqmp_ultra96 + value: 0x80000000 +- enabled-by: true + value: 0x10000000 description: | override a BSP's default RAM length enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optramori.yml b/spec/build/bsps/arm/xilinx-zynqmp/optramori.yml index 401b8ec3a3..082be7e826 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optramori.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optramori.yml @@ -7,9 +7,10 @@ actions: - format-and-define: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 1048576 -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00100000 description: '' enabled-by: true format: '{:#010x}' diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optresetvec.yml b/spec/build/bsps/arm/xilinx-zynqmp/optresetvec.yml index efd1ea2b2a..206a6f2801 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/optresetvec.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/optresetvec.yml @@ -4,9 +4,10 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: false -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: false description: | reset vector address for BSP start enabled-by: true |