diff options
Diffstat (limited to '')
19 files changed, 425 insertions, 0 deletions
diff --git a/spec/build/bsps/arm/altera-cyclone-v/abi.yml b/spec/build/bsps/arm/altera-cyclone-v/abi.yml new file mode 100644 index 0000000000..a3a710c97d --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/abi.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- split: null +- env-append: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: +- -march=armv7-a +- -mthumb +- -mfpu=neon +- -mfloat-abi=hard +- -mtune=cortex-a9 +default-by-variant: [] +description: | + ABI flags +enabled-by: true +links: [] +name: ABI_FLAGS +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml new file mode 100644 index 0000000000..abe3d7f490 --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml @@ -0,0 +1,142 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: arm +bsp: altcycv_devkit +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +enabled-by: true +family: altera-cyclone-v +includes: [] +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/arm/altera-cyclone-v/include/bsp.h + - bsps/arm/altera-cyclone-v/include/tm27.h +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h + - bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h + - bsps/arm/altera-cyclone-v/include/bsp/hwlib.h + - bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h + - bsps/arm/altera-cyclone-v/include/bsp/irq.h +- destination: ${BSP_INCLUDEDIR}/bsp/socal + source: + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h + - bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h +- destination: ${BSP_LIBDIR} + source: + - bsps/arm/altera-cyclone-v/start/linkcmds + - bsps/arm/altera-cyclone-v/start/linkcmds.altcycv +links: +- role: build-dependency + uid: abi +- role: build-dependency + uid: objsmp +- role: build-dependency + uid: opta9periphclk +- role: build-dependency + uid: optcachedata +- role: build-dependency + uid: optcacheinst +- role: build-dependency + uid: optclkfastidle +- role: build-dependency + uid: optconcfg +- role: build-dependency + uid: optconuart1 +- role: build-dependency + uid: optfdtcpyro +- role: build-dependency + uid: optfdten +- role: build-dependency + uid: optfdtmxsz +- role: build-dependency + uid: optfdtro +- role: build-dependency + uid: optfdtuboot +- role: build-dependency + uid: opti2cspeed +- role: build-dependency + uid: optnoi2c +- role: build-dependency + uid: optresetvec +- role: build-dependency + uid: optuartbaud +- role: build-dependency + uid: optuartirq +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: ../../bspopts +source: +- bsps/arm/altera-cyclone-v/console/console-config.c +- bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_16550_uart.c +- bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_address_space.c +- bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_clock_manager.c +- bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_dma.c +- bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_dma_program.c +- bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_generalpurpose_io.c +- bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_i2c.c +- bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_qspi.c +- bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_reset_manager.c +- bsps/arm/altera-cyclone-v/i2c/i2cdrv-config.c +- bsps/arm/altera-cyclone-v/i2c/i2cdrv.c +- bsps/arm/altera-cyclone-v/rtc/rtc.c +- bsps/arm/altera-cyclone-v/start/bspclean.c +- bsps/arm/altera-cyclone-v/start/bspgetworkarea.c +- bsps/arm/altera-cyclone-v/start/bspreset.c +- bsps/arm/altera-cyclone-v/start/bspstart.c +- bsps/arm/altera-cyclone-v/start/bspstarthooks.c +- bsps/arm/altera-cyclone-v/start/mmu-config.c +- bsps/arm/shared/cache/cache-l2c-310.c +- bsps/arm/shared/clock/clock-a9mpcore.c +- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c +- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c +- bsps/arm/shared/irq/irq-gic.c +- bsps/arm/shared/start/bsp-start-memcpy.S +- bsps/shared/dev/btimer/btimer-stub.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/rtc/rtc-support.c +- bsps/shared/dev/serial/console-termios-init.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/irq/irq-default-handler.c +- bsps/shared/start/bsp-fdt.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/objsmp.yml b/spec/build/bsps/arm/altera-cyclone-v/objsmp.yml new file mode 100644 index 0000000000..bf0c99d21f --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/objsmp.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +cxxflags: [] +enabled-by: +- RTEMS_SMP +includes: [] +install: [] +links: [] +source: +- bsps/arm/altera-cyclone-v/start/bspsmp.c +- bsps/arm/shared/start/arm-a9mpcore-smp.c +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml b/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml new file mode 100644 index 0000000000..e67ddc129b --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: false +default-by-variant: [] +description: | + define to set ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz, otherwise alt_clk_freq_get() is used +enabled-by: true +links: [] +name: BSP_ARM_A9MPCORE_PERIPHCLK +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml b/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml new file mode 100644 index 0000000000..77dac09116 --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + enable data cache +enabled-by: true +links: [] +name: BSP_DATA_CACHE_ENABLED +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml b/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml new file mode 100644 index 0000000000..a59db43f31 --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + enable instruction cache +enabled-by: true +links: [] +name: BSP_INSTRUCTION_CACHE_ENABLED +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml new file mode 100644 index 0000000000..b800b20428 --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: false +default-by-variant: +- value: true + variants: + - arm/.*qemu +description: | + This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing. This can significantly reduce simulation times. +enabled-by: true +links: [] +name: CLOCK_DRIVER_USE_FAST_IDLE +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml b/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml new file mode 100644 index 0000000000..635697cc8a --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + configuration for console (UART 0) +enabled-by: true +links: [] +name: CYCLONE_V_CONFIG_CONSOLE +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml b/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml new file mode 100644 index 0000000000..f5c588a330 --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + configuration for UART 1 +enabled-by: true +links: [] +name: CYCLONE_V_CONFIG_UART_1 +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdtcpyro.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdtcpyro.yml new file mode 100644 index 0000000000..c26b1ae051 --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdtcpyro.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + copy the FDT blob into the read-only load area via bsp_fdt_copy() +enabled-by: true +links: [] +name: BSP_FDT_BLOB_COPY_TO_READ_ONLY_LOAD_AREA +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml new file mode 100644 index 0000000000..f2fc473967 --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + define if FDT is supported +enabled-by: true +links: [] +name: BSP_FDT_IS_SUPPORTED +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdtmxsz.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdtmxsz.yml new file mode 100644 index 0000000000..14af766230 --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdtmxsz.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 262144 +default-by-variant: [] +description: | + maximum size of the FDT blob in bytes +enabled-by: true +format: '{}' +links: [] +name: BSP_FDT_BLOB_SIZE_MAX +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdtro.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdtro.yml new file mode 100644 index 0000000000..a61bb2924b --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdtro.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + place the FDT blob into the read-only data area +enabled-by: true +links: [] +name: BSP_FDT_BLOB_READ_ONLY +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdtuboot.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdtuboot.yml new file mode 100644 index 0000000000..5805e912ff --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdtuboot.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + copy the U-Boot provided FDT to an internal storage +enabled-by: true +links: [] +name: BSP_START_COPY_FDT_FROM_U_BOOT +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml b/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml new file mode 100644 index 0000000000..ee8097aa3b --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 100000 +default-by-variant: [] +description: | + speed for I2C0 in HZ +enabled-by: true +format: '{}' +links: [] +name: CYCLONE_V_I2C0_SPEED +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml b/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml new file mode 100644 index 0000000000..2d36d5f930 --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + Number of configured I2C buses. Note that each bus has to be configured in an apropriate i2cdrv_config array. +enabled-by: true +links: [] +name: CYCLONE_V_NO_I2C +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml b/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml new file mode 100644 index 0000000000..efd1ea2b2a --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: false +default-by-variant: [] +description: | + reset vector address for BSP start +enabled-by: true +links: [] +name: BSP_START_RESET_VECTOR +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml b/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml new file mode 100644 index 0000000000..b5f577ffc3 --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: 115200 +default-by-variant: [] +description: | + baud for UARTs +enabled-by: true +format: '{}' +links: [] +name: CYCLONE_V_UART_BAUD +type: build diff --git a/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml b/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml new file mode 100644 index 0000000000..152668b2d9 --- /dev/null +++ b/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: true +default-by-variant: [] +description: | + enable usage of interrupts for the UART modules +enabled-by: true +links: [] +name: BSP_USE_UART_INTERRUPTS +type: build |