diff options
Diffstat (limited to '')
13 files changed, 0 insertions, 13 deletions
diff --git a/spec/build/bsps/arm/altera-cyclone-v/abi.yml b/spec/build/bsps/arm/altera-cyclone-v/abi.yml index 7a52d2c74d..a3a710c97d 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/abi.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/abi.yml @@ -12,7 +12,6 @@ default: - -mfpu=neon - -mfloat-abi=hard - -mtune=cortex-a9 -default-by-family: [] default-by-variant: [] description: | ABI flags diff --git a/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml b/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml index 9e091ec2c4..e67ddc129b 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: false -default-by-family: [] default-by-variant: [] description: | define to set ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz, otherwise alt_clk_freq_get() is used diff --git a/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml b/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml index a37ac80f89..77dac09116 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true -default-by-family: [] default-by-variant: [] description: | enable data cache diff --git a/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml b/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml index fe2e044f5d..a59db43f31 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true -default-by-family: [] default-by-variant: [] description: | enable instruction cache diff --git a/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml index 661d94afe3..b800b20428 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: false -default-by-family: [] default-by-variant: - value: true variants: diff --git a/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml b/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml index 00d7a4ea92..635697cc8a 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true -default-by-family: [] default-by-variant: [] description: | configuration for console (UART 0) diff --git a/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml b/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml index 15a4ff3142..f5c588a330 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true -default-by-family: [] default-by-variant: [] description: | configuration for UART 1 diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml index 28663616df..f2fc473967 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true -default-by-family: [] default-by-variant: [] description: | define if FDT is supported diff --git a/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml b/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml index 8053c93c47..ee8097aa3b 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: 100000 -default-by-family: [] default-by-variant: [] description: | speed for I2C0 in HZ diff --git a/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml b/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml index a4540d0e4b..2d36d5f930 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true -default-by-family: [] default-by-variant: [] description: | Number of configured I2C buses. Note that each bus has to be configured in an apropriate i2cdrv_config array. diff --git a/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml b/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml index 52f469c2d9..efd1ea2b2a 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: false -default-by-family: [] default-by-variant: [] description: | reset vector address for BSP start diff --git a/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml b/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml index abd3502e5c..b5f577ffc3 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: 115200 -default-by-family: [] default-by-variant: [] description: | baud for UARTs diff --git a/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml b/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml index 3f264d3cbb..152668b2d9 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml @@ -6,7 +6,6 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true -default-by-family: [] default-by-variant: [] description: | enable usage of interrupts for the UART modules |