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-rw-r--r--doc/supplements/sparc/cpumodel.t2
-rw-r--r--doc/supplements/sparc/cpumodel.texi2
2 files changed, 2 insertions, 2 deletions
diff --git a/doc/supplements/sparc/cpumodel.t b/doc/supplements/sparc/cpumodel.t
index af1605572c..85afb3f48f 100644
--- a/doc/supplements/sparc/cpumodel.t
+++ b/doc/supplements/sparc/cpumodel.t
@@ -141,7 +141,7 @@ The code required to enter low power mode is CPU model specific.
@end ifinfo
@section CPU Model Implementation Notes
-The ERC is a custom SPARC V7 implementation based on the Cypress 601/602
+The ERC32 is a custom SPARC V7 implementation based on the Cypress 601/602
chipset. This CPU has a number of on-board peripherals and was developed by
the European Space Agency to target space applications. RTEMS currently
provides support for the following peripherals:
diff --git a/doc/supplements/sparc/cpumodel.texi b/doc/supplements/sparc/cpumodel.texi
index af1605572c..85afb3f48f 100644
--- a/doc/supplements/sparc/cpumodel.texi
+++ b/doc/supplements/sparc/cpumodel.texi
@@ -141,7 +141,7 @@ The code required to enter low power mode is CPU model specific.
@end ifinfo
@section CPU Model Implementation Notes
-The ERC is a custom SPARC V7 implementation based on the Cypress 601/602
+The ERC32 is a custom SPARC V7 implementation based on the Cypress 601/602
chipset. This CPU has a number of on-board peripherals and was developed by
the European Space Agency to target space applications. RTEMS currently
provides support for the following peripherals: